+

William Stallings
Computer Organization
and Architecture
9th Edition
+
Chapter 3
A Top-Level View of Computer
Function and Interconnection
+
Computer Components
 Contemporary computer designs are based on concepts developed by
John von Neumann at the Institute for Advanced Studies, Princeton

 Referred to as the von Neumann architecture and is based on three

key concepts:
 Data and instructions are stored in a single read-write memory
 The contents of this memory are addressable by location, without regard to
the type of data contained there
 Execution occurs in a sequential fashion (unless explicitly modified) from
one instruction to the next

 Hardwired program
 The result of the process of connecting the various components in the
desired configuration
+
Hardware
and Software
Approaches
 Software
• A sequence of codes or instructions
• Part of the hardware interprets each instruction and Software
generates control signals
• Provide a new sequence of codes for each new
program instead of rewiring the hardware
Major components:
• CPU I/O
• Instruction interpreter Components
• Module of general-purpose arithmetic and logic
functions
• I/O Components
• Input module
+
• Contains basic components for accepting data and
instructions and converting them into an internal
form of signals usable by the system
• Output module
• Means of reporting results
 MEMORY
Memory address Memory buffer
register (MAR) register (MBR)
• Specifies the • Contains the data
address in memory to be written into
for the next read or memory or
write receives the data
read from memory
MAR

I/O address I/O buffer

register (I/OAR) register (I/OBR)
+ • Specifies a • Used for the
particular I/O exchange of data
device between an I/O
module and the MBR
CPU
 Computer
Components:
Top Level
View
+
Basic Instruction Cycle
+
Fetch Cycle
 At the beginning of each instruction cycle the processor fetches an
instruction from memory

 The program counter (PC) holds the address of the instruction to be

fetched next

 The processor increments the PC after each instruction fetch so that

it will fetch the next instruction in sequence

 The fetched instruction is loaded into the instruction register (IR)

 The processor interprets the instruction and performs the required

action
Action Categories

• Data transferred from •Data transferred to

processor to memory or from or from a peripheral
memory to processor device by
transferring between
the processor and an
I/O module

Processor- Processor-
memory I/O

Data
Control
processing

• An instruction may specify • The processor may

that the sequence of perform some
execution be altered arithmetic or logic
operation on data
+
+
Example
of
Program
Execution
+
Instruction Cycle State Diagram
+
Classes of Interrupts
Program Flow Control
+
Transfer of Control via Interrupts
+
Instruction Cycle With Interrupts
+

Program
Timing:
Short I/O
Wait
+

Program
Timing:
Long I/O
Wait
Instruction Cycle State Diagram
With Interrupts
 Transfer of
Control

Multiple
Interrupts

+
+ Time Sequence of Ex
Multiple Interrupts am
ple
+
I/O Function
 I/O module can exchange data directly with the processor

 Processor can read data from or write data to an I/O module

 Processor identifies a specific device that is controlled by a particular I/O
module
 I/O instructions rather than memory referencing instructions

 In some cases it is desirable to allow I/O exchanges to occur directly

with memory
 The processor grants to an I/O module the authority to read from or write
to memory so that the I/O memory transfer can occur without tying up the
processor
 The I/O module issues read or write commands to memory relieving the
processor of responsibility for the exchange
 This operation is known as direct memory access (DMA)
+ Computer
Modules
The interconnection structure must support the following
types of transfers:

Memory Processor I/O to or

I/O to Processor
to to from
processor to I/O
processor memory memory

An I/O
module is
allowed to
exchange
Processor
Processor data directly
reads an Processor Processor
reads data with memory
instruction writes a unit sends data to
from an I/O without
or a unit of of data to the I/O
device via an going
data from memory device
I/O module through the
memory
processor
using direct
memory
access
A communication pathway Signals transmitted by any one
connecting two or more device are available for
devices
• Key characteristic is that it is a shared
reception by all other devices
attached to the bus
Bus
transmission medium • If two devices transmit during the same
time period their signals will overlap
and become garbled
Inter
conn
Typically consists of multiple Computer systems contain a
ectio
communication lines
• Each line is capable of transmitting
signals representing binary 1 and
number of different buses that
provide pathways between n
binary 0
components at various levels
of the computer system
hierarchy

System bus
• A bus that connects major computer The most common computer
components (processor, memory, I/O)
interconnection structures are
based on the use of one or
more system buses
Data Bus
 Data lines that provide a path for moving data among system
modules

 May consist of 32, 64, 128, or more separate lines

 The number of lines is referred to as the width of the data bus

 The number of lines determines how many bits can be transferred at a

time

 The width of the data bus

is a key factor in
determining overall
system performance
+ Address Bus Control Bus

 Used to designate the source or  Used to control the access and the
destination of the data on the data bus use of the data and address lines
 If the processor wishes to read a
word of data from memory it puts
 Because the data and address lines
the address of the desired word on are shared by all components there
the address lines must be a means of controlling their
use
 Width determines the maximum
possible memory capacity of the  Control signals transmit both
system command and timing information
among system modules
 Also used to address I/O ports
 Timing signals indicate the validity
 The higher order bits are used to
of data and address information
select a particular module on the
bus and the lower order bits select  Command signals specify operations
a memory location or I/O port
to be performed
within the module
Bus Interconnection Scheme
 Typical control lines
• Memory write: causes data on the bus to be written into the addressed location
• Memory read: causes data from the addressed location to be placed on the bus
• I/O write: causes data on the bus to be output to the addressed I/O port
• I/O read: causes data from the addressed I/O port to be placed on the bus
• Transfer ACK: indicates that data have been accepted from or placed on the bus
• Bus request: indicates that a module needs to gain control of the bus
• Bus grant: indicates that a requesting module has been granted control of the bus
• Interrupt request: indicates that an interrupt is pending
• Interrupt ACK: acknowledges that the pending interrupt has been recognized
• Clock: is used to synchronize operations
• Reset: initializes all modules.
Bus
Conf
igura
tions
+
Elements of Bus Design
 Timing of
Synchronous
Bus Operations
 Timing of
Asynchronous
Bus
Operations
+
Point-to-Point Interconnect

Principal reason for change was At higher and higher data rates
the electrical constraints it becomes increasingly difficult
encountered with increasing the to perform the synchronization
frequency of wide synchronous and arbitration functions in a
buses timely fashion

A conventional shared bus on

the same chip magnified the
difficulties of increasing bus Has lower latency, higher data
data rate and reducing bus rate, and better scalability
latency to keep up with the
processors
+Quick Path Interconnect
QPI
 Introduced in 2008

 Multiple direct connections

 Direct pairwise connections to other components eliminating the
need for arbitration found in shared transmission systems

 Layered protocol architecture

 These processor level interconnects use a layered protocol
architecture rather than the simple use of control signals found in
shared bus arrangements

 Packetized data transfer

 Data are sent as a sequence of packets each of which includes
control headers and error control codes
 Multicore
Configuration
Using
QPI
QPI Layers
+
Physical Interface of the Intel QPI
Interconnect
+
QPI Multilane Distribution
+
QPI Link Layer

 Flow control function

 Performs two key functions:  Needed to ensure that a sending
flow control and error control QPI entity does not overwhelm a
 Operate on the level of the receiving QPI entity by sending
flit (flow control unit) data faster than the receiver can
 Each flit consists of a 72- process the data and clear buffers
for more incoming data
bit message payload and an
8-bit error control code
called a cyclic redundancy  Error control function
check (CRC)
 Detects and recovers from bit
errors, and so isolates higher
layers from experiencing bit
errors
+
QPI Routing and Protocol Layers

Routing Layer Protocol Layer

 Packet is defined as the unit of
 Used to determine the course that a transfer
packet will traverse across the
available system interconnects  One key function performed at this
level is a cache coherency protocol
 Defined by firmware and describe which deals with making sure that
the possible paths that a packet can main memory values held in
follow multiple caches are consistent

 A typical data packet payload is a

block of data being sent to or from
a cache
+
Peripheral Component Interconnect
(PCI)
 A popular high bandwidth, processor independent bus that can function
as a mezzanine or peripheral bus

 Delivers better system performance for high speed I/O subsystems

 PCI Special Interest Group (SIG)

 Created to develop further and maintain the compatibility of the PCI
specifications

 PCI Express (PCIe)

 Point-to-point interconnect scheme intended to replace bus-based schemes such as
PCI
 Key requirement is high capacity to support the needs of higher data rate I/O
devices, such as Gigabit Ethernet
 Another requirement deals with the need to support time dependent data streams
+
PCIe
Configuration
+
PCIe Protocol Layers
+
PCIe Multilane Distribution
 PCIe
Transmit
and Receive
Block
Diagrams
+ Receives read and write requests from the

software above the TL and creates request
packets for transmission to a destination via
the link layer

PCIe  Most transactions use a split transaction

technique
Transaction Layer (TL)  A request packet is sent out by a source
PCIe device which then waits for a
response called a completion packet

 TL messages and some write transactions

are posted transactions (meaning that no
response is expected)

 TL packet format supports 32-bit

memory addressing and extended 64-bit
memory addressing
+
The TL supports four address spaces:

 Memory  I/O
 The memory space includes  This address space is used for
system main memory and PCIe legacy PCI devices, with
I/O devices reserved address ranges used to
 Certain ranges of memory address legacy I/O devices
addresses map into I/O devices

 Configuration  Message
 This address space enables the  This address space is for control
TL to read/write configuration signals related to interrupts,
registers associated with I/O error handling, and power
devices management
PCIe TLP Transaction Types
+

PCIe
Protocol
Data
Unit
Format
+
TLP Memory Request Format
+ Summary A Top-Level View of
Computer Function and
Interconnection
Chapter 3
 Point-to-point interconnect
 Computer components
 QPI physical layer
 Computer function
 QPI link layer
 Instruction fetch and execute
 QPI routing layer
 Interrupts
 QPI protocol layer
 I/O function
 Interconnection structures  PCI express
 Bus interconnection  PCI physical and logical
 Bus structure architecture
 Multiple bus hierarchies  PCIe physical layer
 Elements of bus design  PCIe transaction layer
 PCIe data link layer