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Roba Multiplier

This document outlines a proposed RoBA (Rounding-Based Approximate) multiplier system. The RoBA multiplier offers advantages over existing multiple constant multiplier techniques such as lower power consumption, reduced delay, smaller logic size and reduced chip area. It allows common hardware to be used for both signed and unsigned multiplications. The design is developed in Verilog HDL and synthesized in Xilinx. Simulation results show the RoBA multiplier offers lower delay, power and area compared to Wallace and HAAM multipliers. Potential applications include image and signal processing. Future work may involve implementing the design in FPGAs and further optimization.

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Nishitha Nishi
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80 views

Roba Multiplier

This document outlines a proposed RoBA (Rounding-Based Approximate) multiplier system. The RoBA multiplier offers advantages over existing multiple constant multiplier techniques such as lower power consumption, reduced delay, smaller logic size and reduced chip area. It allows common hardware to be used for both signed and unsigned multiplications. The design is developed in Verilog HDL and synthesized in Xilinx. Simulation results show the RoBA multiplier offers lower delay, power and area compared to Wallace and HAAM multipliers. Potential applications include image and signal processing. Future work may involve implementing the design in FPGAs and further optimization.

Uploaded by

Nishitha Nishi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 23

CONTENTS :-

1. Motivation Behind this project


2. Literature review
3. Existing system
4. Proposed system
5. Introduction
6. Software required
7. Algorithm
8. Block Diagram
9. Advantages
10. Disadvantages
11. Applications
12. Simulation Results
13. Future scope & Conclusion
14. References
Motivation Behind this project
1. Technology is developed with the aim to efficiently
serve the computation.
2. Multiplier is a very basic building block of arithmetic
Logic Unit and would be a limiting factor in
performance of devices.
3. Therefore, it is important to develop the
computational structures that are optimized and
suitable for the current technology
LITERATURE REVIEW
Author Name Work Outcome
R.Zendegani RoBA Multiplier Applicable
to both signed and
unsigned multiplications

S. Vahdat Rounding Based Scalable Improves delay, area, and


Approximate Multiplier energy consumption up
to 41%, 90%, and 98%
respectively

Tiankai Su Integer multiplication Accurate in Deletion,


by output D-truncation, and
truncation Truncation with
Rounding
LITERATURE REVIEW(continued)
Author Name Work Outcome
M. J. Schulte Polynomial Computational delay by
approximation 5% to 30% and the area
requirements by 33% to
77%

P.Lohray Conventional Wallace Accuracy for each range


tree accurate multiplier of the data with
minimum cost on
the hardware

E. Hosseini Low power unsigned Power consumption


Multiplication structure is 41mW
EXISTING SYSTEM
1. The existing multiplier is multiple constant
multiplier(MCM)
2. But the drawback is MCM technique will not work
both for signed and un-signed operation, so we need
to design separate MCM for signed and unsigned
multiplication.
3. It consumes more power and delay is also more
4. More logic size
5. It occupies more chip area
PROPOSED SYSTEM
1. RoBA multiplier(Rounding Based Approximate
Multiplier ) is the proposed system
2. we can use common multiplier for both signed and
unsigned
3. It consumes less power and less delay
4. It has less logic size.
5. It occupies less chip area
INTRODUCTION
1. Energy minimization is one of the main design
requirements in almost any electronic systems,
especially the portable ones such as smart phones,
tablets and different gadgets.
2. Digital signal processing blocks are key components
of these portable devices for realizing various
multimedia applications.
3. The computational core of these blocks is the
arithmetic logic unit where multiplications have the
greatest share among all arithmetic operations
SOFTWARE REQUIRED
SOFTWARE:
1. XILINX
2. Verilog HDL

The design was developed in verilog HDL and


synthesized in Xilinx
ALGORITHM
1. The numbers must be in the 2’s complement form
2. The numbers should be rounded to nearest values
of 2n
3. The multiplication of A*B is written as
A*B = (Ar-A)*(Br-B)+(Ar*B)+(Br*A)-(Ar*Br)
4. The multiplication of (Ar*Br), (Ar*B) and (Br*A) can
be implemented by shift operation.
5. The hardware implementation of (Ar-A)*(Br-B) is
rather complex and the weight of this term in the
final result is typically small.
ALGORITHM(Contd.)
6. Hence, RoBA multiplier is implemented by

A*B = (Ar*B)+(Br*A)-(Ar*Br)
7.This can be performed by just using three shifters, one
adder and one subtractor
8. If ( Ar < A and Br > B ) or (Ar > A and Br < B )the final
result will be larger than the exact result
9.If (Ar < A and Br < B) or (Ar > A and Br > B) the final
result will be smaller then the exact result
BLOCK DIAGRAM
Br*A
Shifter

A Ar
Sign Sign
Round Shifter Adder Subtractor
detect set
ing
B or A*B
Br

Shifter
Ar*B
SIGN DETECTOR: It detects the sign of the input
values. It extracts the most significant bit(MSB) of the
input value
MSB – 0 (+ve)
MSB – 1 (-ve)
ROUNDING : This block rounds off the input values to
the nearest value of 2
SHIFTER : we use shifters to perform the multiplication
operation by shifting.
ADDERS: we use ripple carry adders
SIGN SET: The main function of the sign set block is to
set the sign of final multiplication result
Comparison Of Various Multipliers
MULTIPLIERS DELAY POWER AREA
(NANO SECONDS) (MILLI WATTS) (MICRO METER
SQUARE)
ROBA 1.12 5.37 13324
MULTIPLIER

WALLACE 1.69 17.3 33124


MULTIPLIER

HAAM 2.59 17.58 23194


MULTIPLIER
ADVANTAGES
1. Common multiplier for signed and unsigned
multiplications.
2. Less logic size.
3. Low power consumption
4. Less delay
5. Design complexity is less
6. Occupies less area in the order of 13224(micrometer
Square)
7. Computational time is less
8. Requires less number of LUTS
DISADVANTAGES
The computational intensive part of the
multiplication is omitted improving speed and energy
conservation at a price of small error.
APPLICATIONS
1. Can be used in various image processing applications
like Image sharpening , Image smoothing
2. Voice smoothing
3. Digital signal processing
4. FIR filters
5. Fast Fourier transform(FFT)
SIMULATION RESULTS :
Simulation results:
Technology Schematic
RTL Schematic
Conclusion And Future Scope
This low power, fast and area efficient multiplier
can be used for FIR filter design, MAC design as an
extension to this one. The hardware implementations
of the approximate multiplier can be downloaded into
FPGA for further improvements and observation.
REFERENCES
1. https://ieeexplore.ieee.org/document/7517375
2. https://www.researchgate.net/publication/
305485438_RoBA_Multiplier_A_Rounding-
Based_Approximate_Multiplier_for_High-
Speed_yet_Energy-
Efficient_Digital_Signal_Processing
3. http://www.kresttechnology.com/krest-academic-
projects/krest-mtech-projects/ECE/M-TECH
%20VLSI%202018-19/basepapers/48.pdf
THANK YOU
ANY QUERIES??

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