Digital VLSI Design

T.Rajeswari (IN1729)
Anusha G (IN1727)

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©2022 The information in this document is the property of Quest Global Services Private Limited and may not be disclosed in any manner to a third party nor used for any purpose other than that for which it is supplied without prior written consent.
 Introduction

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 Outline of the course:

Motivation

Building a chip

Basics of design automation

Overview of chip design flow

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 Motivation

The integrated circuit – 1964 The intel 4004, 2300 transistors – 1971 Intel 486DX2 1.2M transistors-1992

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 Features of Core i7-6950X

Core i7-6950X Extreme Edition(Broadwell-E)

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 Moore’s law
It is the observation that the number of transistors in a dense integrated circuit (IC) doubles
about every two years.Moore's law is an observation and projection of a historical trend.

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 The observation is named after Gordon Moore, the co-founder of Fairchild Semiconductor and
Intel (and former CEO of the latter), who in 1965 posited a doubling every year in the number of
components per integrated circuit,[a] and projected this rate of growth would continue for at least
another decade.
Moore's prediction has been used in the semiconductor industry to guide long-term planning and
to set targets for research and development, thus functioning to some extent as a self-fulfilling
prophecy.
Advancements in digital electronics, such as the reduction in quality-adjusted microprocessor
prices, the increase in memory capacity (RAM and flash), the improvement of sensors, and even
the number and size of pixels in digital cameras, are strongly linked to Moore's law. These
ongoing changes in digital electronics have been a driving force of technological and social
change, productivity, and economic growth.
Industry experts have not reached a consensus on exactly when Moore's law will cease to apply.
Microprocessor architects report that semiconductor advancement has slowed industry-wide
since around 2010, slightly below the pace predicted by Moore's law.

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 Theoretical system on a chip
Here is the block diagram:

All these different things we

can integrated on one chip is
really complicated so how on
earth should we design such a
thing ?

To overcome this we have a

solution.

That are divide into 3 parts.

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 Design Abstraction:
If we want to abstract away each part of design of our engineering task and each factor,
in each team of engineers is specializes in one part of it, but we can get input from other
engineers and we give output to other engineers, we can specialize in our one part and
do it the best and we can deal with the bigger problems by connecting all those different
abstractions together so, design abstraction is key to solve such a problem.

Design Automation:

If we are part of dealing with many transistors and this is very difficult functionality, there
we need to make automation and we need to use our computers to work for us and help
us more out of what we can do. So design automation we can often call as EDA(electric
design automation). It is a key part to how we can deal with this problem.

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 Design Re-Use(IP)

It is also known as IP or intellecetual propety and design re-use means that if

somebody already has design something why dont we just use it instead of trying
to design everything ourselves, so that can either be going and buying or
designing it inside our company by a different team.

Design reuse can expedite system-on-chip (SoC) and IC design and

development. But managing the increasingly large number of digital assets is
difficult. It creates a need for stronger collaboration between internal and external
resources.

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 Building a chip
General Design Approach: Partition

Model/Solution
How do engineers build a bridge?

Divide and conquer !!! Tools/Interface

Here we start with the design by partitioning and Verify/Validate

next we will define a model for the design or the problem
and then we will use different tools and some design
automations. Then it is important that we should verify and Develop flow
validate the design and then at last connect everthing an we
need to connect everything and check the design.
Then we should check what doen’t work and should
start
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over.
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 Basic design abstraction

System level Another View:

Application Register transfer level

Register Transfer level

Algorithm Circuits

Gate level programming language Devices

Transistor level OS/Virtual machine Physics

Layout level Architeture

Mask level Micro-Architeture

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 System level
It means the amount of complexity by which a system is viewed or programmed.The higher the
level, the less detail. The lower the level, the more detail.

Here we have some type of algorithm or application.

Here we will describe it for high level with a C or any other programming language and we
should abstarct it.Because it doesn’t have any implementation or any timing inside and very
efficient to start up and should make a execution model of the first design so that it shows us that
how it is going to work and what it is going to do and also it is very difficult to remain the same
because in this there is no link to implementation.
E.g:
Port* compute_optimal_route_for_packet
( Packet_t *packet, Channel_t *channel)
{
static Queue_t *packet_queue;
packet_queue = add_packet(packet_queue, packet);
...
}

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 Register transfer level
It is also calld as RTL.
It is used in hardware description languages like Verilog and VHDL to create high-level
representations of a circuit, from which lower-level representations and ultimately actual wiring
can be derived. Design at the RTL level is typical practice in modern digital design.
RTL is very close to the hardware implementation.
Here we use bit vector data and operations.
e.g:
module ckt(q,a,b,clk);
input a,b,clk;
output q;
wire din;
reg[31:0] q;
assign din=((~q)&(a|b))|((~a)&b);
always@(posedge clk)
q<=din;

endmodule

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 Gate level
This is the lowest level of abstraction.
Here to make this gate level we need to use register transfer level so, by taking some static
machine we turn these into logic gates.

e.g:
So, here we can see the NAND gates and
also the flip-flops here they will carry out
whatever we wrote in the register transfer
level by using the Boolean logic

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 Transistor level
In this transistor level we take a compact level and run thorough simulation of the circuit
and also helps us to build gates.

Layout level
By using transistors it will design the actual layers
that they will be connected together.

Mask level
In this we take the layouts and create photographical
mask which we can be use to do fabrication.

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 In olden days...

The original
Tape-out

Main frame CAD System(1967)

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 Design Automation

Design Analysis and verification

High-level synthesis Functional verification
Logic synthesis Clock domain crossing
Schematic capture Formal verification
Layout Equivalence checking
PCB design Static timing analysis
Physical verifiction
Simulation
Vadilation
Transistor simulation ATPG
Logic simulation BIST
Hardware emulation Mask preparation
Technology CAD OPC
Fields solvers
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 The chip design flow
How a chip is built

Definition and planning Sign-off and Tape-out

Design and verification Silicon validation

Logic synthesis

Physical design and implementation

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 Definition and planning

There are many different design documents that you can hear from our mangement and
marketing andd so far.. we can usually start with a

Marketing requirements document

Chip Architecture
In this we will have the buses, the connectivity partitions, diff.functionality, bandwidth,
power, frequency, hardware vs software

Deign documents
For each block we can make the document which is disscuss in the design with small
enough sub-partitions and actually start drawing with state machine diff.kind of wave-
forms which we expect to see in the actual design.

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 Board requirements

In this we will discuss about the board requirements, size of chip and how the floorplan
is going to be setout

Fabrication
The most important step in the process is fabrication.
There are diff.type of processess they can from diff.prices which has diff.features and
diff.specifications based upon that we will decide what type of process we are going to
use, which has lot of effect on the actual performance and specification of our chip.

At last we go to the project kick-off - transfer to implementation

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 Design and verification

1. RTL (Register transfer level):

In this we descibe the design in verilog or VHDL or something similar that will be
disscussed in next

2. Integartion or development of IP’s:

We take the IP’s from dif.team and we integrate them with rest of our chip

3. synthesability checks:
Linting is the automated checking of your source code for programmatic and stylistic
errors. This is done by using a lint tool (otherwise known as linter). A lint tool is a basic
static code analyzer.

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 4. Formal verification:
We do formal verification actually checking of every single thing inside a certain block
whether we did according to the mathematical models or not.

5. Functional verification of all IP’s :

1. unit level
2. sub-system level
3. chip(SOC) level

Unit level:
A module is verified in it’s own test environment to prove that logic, control,
data paths are functionally correct or not. The goal of the unit level verification is to
ensure that unit/components been tested and conforms to its specifications and ready
to integrated with other sub components of the product.

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 Sub-system level:
Once the components are verified and integrated into sub-systems.
These higher level assemblies are also individually verified before integrated with others
to produce larger assemblies untill the complete system has been integrated and
verified.

Chip(SOC) level:
SOC verification is a process in which the design is tested(or verified)
against a given design specification beore the tape-out. This happens along with
development of the design and start from the time of the design architecture defination
happens.

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 IP integration

Soft IP:
It is in RTL fomat these are technology independent synthesizable RTL
discription return using any HDL. These IP’s are modifable and can be extended
funtionally and it takes lot of work to integrate and make it work at our specification we
need.

Hard IP:
These are design exactly for one process and they cannot be modifable easily
from one process to other process and the design functionality implemented in fixed
logic at the gate and signal route level.

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 Prototyping
It is the process of implementing or synthesizing an ASSIC RTL on a platform
comprising one or more FPGA’s.
There are diff.levels of verification in prototype:

1. Specification driven testing

2. Bug driven testing
3. Coverage driven testing
4. Regreesion

FPGA prototyping:
1. Synthesize to FPGA
2. Speeds up the testing where it is possible

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 Hardware Emulation

It is very imp.type of verification nowadays. It is the one of the big box such as cadence
palladium. Which has several 100 cores on it and we can map actual gate level of bit
component may be even a whole chip to these palladiums and actually test the gate
level at diff.speeds.
It has big serves that can emulate entire design.

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 Logic synthesis
It is the process of taking a high level behavioural model and a register transfer level
and turns into actual gate.
It consists of inputs like
1. Technology lib.file
2. RTL file
3. SDC(constraint) file
4. DFT definitions

Output: Gate level netlist

It describes the kind of logic gates we used to implement the RTL and how the
connectivity between them.

Synthesis:
It converts RTL code to generic logic netlist.

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 Technology mapping

We can take logic netlist and with the help of gates which are available in standard cell
lib.for implementation.

Optimization:
We check and meet the timing/area/power constraints.

Post synthesis checks:

We can do all kind of checks at the end.

1. Gate level simulation

2. formal verification
3. STA
4. Power or area estimation

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 Physical design(back-end)
From our logic synthesis we have gate level netlist and we can start doing our physical
implementation of our back-end in our P.D.

Floorplan
I/O ring
Powerplan
Placement
CTS
Route
DRC, LVS
LEC, post layout

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 Physical implementation inputs
Front end Vendors Foundary
Spec standard cells device models
Architecture memory compiler tech file
RTL I/O’s design rules
Verification hard IP’s

PHYSICAL DESIGN(Backend)

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 Back-end flow

RTL synthesizer gate level

SDC ATPG GTL with scan

Standard cells and macros placement placement design

Scan chains CTS design with CTS

Floor plan routing routed design

Power grid, special routing extraction, STA, DRC,

LVS, density, power,
Clock definitions anteenas

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 Sign off and tape-out

Parasitic extraction

STA with signal integrity

DRC or LVS or ERC or DFM

Post layout

Gate level simulation

Power analysis

DFT

Logic equivalence

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 Silicon validation

Here a Chip Manufacturer uses the actual fabricated silicon (Pre-production sample) to
run the software and conduct the Silicon Validation Process.

Pre-silicon vadilation/verification:
Before fabrication, the designs are generally described in HDL language and simulated
on the high-end simulators. Such design modules are synthesized and are transformed
to the gate-level netlists. Several test cases are run on such netlists to check whether
the design behaves functionally correct or not.

Post-silicon vadilation/verification:
Post-silicon validation is deployed to capture the escaped bugs from the pre-silicon
verification phase. This phase also tries to check the functional correctness of the
design but on the real hardware in the actual working environment. When a design
passes from pre-silicon verification, few initial prototypes of the chips are fabricated and
are used as test objects.

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 So this is all about building and designing the chip

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 Thank You

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