Module 9 Combinational Logic
Module 9 Combinational Logic
Module 3
L.G. Arcega
UDM-CET
BINARY INFORMATION
1. DATA
Information that are manipulated to perform some operation/s
Examples:
Arithmetic (adders, counters, etc…) Logic (decoders, etc…)
Shifting (shift register, etc…)
other similar ops (multiplexers, etc…)
2. CONTROL INFORMATION
Provides command signals that supervise operations in the data
section to meet required data processing tasks
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DIGITAL DESIGN OF LOGIC CIRCUITS
Design of digital circuits that perform data-processing operations
Design of control circuits that supervise the operations and their
sequence
Control and Data Processor Interaction
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COMBINATIONAL CIRCUIT
consist of logic gates whose outputs at any given time are
determined by the combining values of the applied inputs using
logic operations
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DESIGN PROCEDURE
The design of a combinational circuit starts from the verbal outline of
the problem or the specification of the problem and culminates in a
logic diagram or set of Boolean equations/functions from which the
logic diagram can be easily obtained.
PROCEDURE:
1. Analyze the problem.
2. From the specification of the circuit, determine the required
number of inputs and outputs, and assign a letter symbol to each.
3. Derive the truth table that defines the required relationship
between inputs and outputs.
4. Obtain the simplified Boolean functions for each output as a
function of the input variable.
5. Draw the logic diagram.
6. Verify the correctness of the design.
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CODE CONVERTER
a circuit that translates information from one binary code to another
INPUTS
provide the bit combination of the elements as specified by the first code
OUTPUTS
generate the corresponding bit combination of the second code
EXAMPLE: Design a logic circuit that can convert 4-bit binary digits in BCD Code to Excess-3 Code.
Decimal digits that can be represented under the BCD coding system.
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Example: Design a combinational circuit with 3 inputs and 1 output.
The output must be logic 1 when the binary value of the inputs is less
than 011(3) and logic 0 otherwise. Use NAND gates only. Assume
that the complement of the signals are directly available.
Input Analysis Output Since according to De Morgan’s law a
Truth Table
X Y Z Row value F NAND gate is equal to a bubbled OR
0 0 0 0 1 NAND Gate No. 1
0 0 1 1 1 (X’Y’)’ = X’’ + Y’’ = X + Y
0 1 0 2 1 For NAND Gate No. 2
0 1 1 3 0 (X’Z’)’ = X’’ + Z’’ = X + Z
1 0 0 4 0 For NAND Gate No. 3
1 0 1 5 0 [(X+Y)][X+Z)]’ = (X+Y)’ + (X+Z)’ =
1 1 0 6 0 X’Y + X’Z’
1 1 1 7 0
L.G. Arcega
Thanks for your time.
PM is the key
L.G. Arcega
UDM-CET