Module 4: Metrics & Methodology Topic 3: Source Synchronous Timing

OGI EE564 Howard Heck

clk

in

Tsetup

Thold

H. Heck 2008

Section 4.3

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Where Are We?

1. 2. 3. 4. Introduction Transmission Line Basics Analysis Tools Metrics & Methodology
1. 2. 3. 4. 5. Synchronous Timing Signal Quality Source Synchronous Timing Recovered Clock Timing Design Methodology

Source Synchronous Timing

5. Advanced Transmission Lines 6. Multi-Gb/s Signaling 7. Special Topics

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Contents
Synchronous Bus Limitations Source Synchronous Concept & Advantages Operation Timing Equations Maximum Transfer Rate Summary References Appendix: Timing Equation Derivation

Source Synchronous Timing

H. Heck 2008

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Common Clock Limitations

clk

Source Synchronous Timing

FROM CORE

f max = 1

Tcycle ,min

Tcycle ,min Tdriver ,max + T flight ,max + Tsetup + Tskew

Max frequency is defined by min cycle time Min cycle time is limited by maximum delays. Can we find a way to remove the dependence on absolute delays?
H. Heck 2008 Section 4.3 4

TO CORE

CLK D Q

CLK D Q

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Source Synchronous Signaling Concept

D Q Data D Q Deskew D Q

PLL

Delay Line

I/O Clock

PLL

Source Synchronous Timing

Sys Clock

Sys Clock

The transmitting agent sends the clock (a.k.a. strobe), along with the data signal. Overview:
Drive the clock and data signals with a known phase relationship. Design the clock and data signals to be identical in order to preserve the phase relationship. As long as the phase relationship can be maintained, the lines can be much longer.
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Source Synchronous Concept Example

Suppose that we transmit a data signal 1 ns prior to transmitting the strobe. Youre given a 500 ps receiver setup requirement. You find that the flight time for the data signal varies between 5.5 ns and 5.7 ns. The flight time for the clock signal also varies between 5.5 ns 5.5 ns and 5.7 ns, independent 1.0 ns CLK/CLK# from the data. @ Tx Can we meet DATA the setup requirement? @ Tx
5.7 ns

Source Synchronous Timing

DATA @ Rx
300 ps

CLK/CLK# @ Rx
H. Heck 2008 Section 4.3

Tsu = 500 ps

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Source Synchronous Advantage

From the preceding example, it should be apparent that source synchronous performance depends on relative, rather than absolute delays.
True for drivers and interconnect, though we must still meet the absolute setup/hold requirements for the receiver.

Source Synchronous Timing

In real systems, the difference in delay between signals can be made much smaller than the absolute delays. Therefore, with source synchronous signaling we can expect
to achieve higher performance to be able to use longer traces

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Transfer Rate Comparison

Synchronous FSB Graphics Memory 200 MHz 66 MHz 133 MHz Source Synchronous 1600 MT/s 533 MT/s 1600 MT/s 800 MT/s (RDRAM)

Source Synchronous Timing

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Operation
Typically, there is one strobe signal (or pair of signals) per two bytes of data signals.
Varies by design
PLL

Data

Deskew

Delay Line

I/O Clock

90o

PLL

Sys Clock

Sys Clock

Source Synchronous Timing

Data

Deskew

Signal relationships at the transmitter are shown below.

CLK

PLL

Delay Line

I/O Clock

PLL

Sys Clock

Sys Clock

DATA
Setup Hold Setup Hold

STROBE

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Source Synchronous Operation

@ RECEIVER

Source Synchronous Timing

STROBE/STROBE

Tsumar Tsuskew Tvb

Tsu Th Thskew Tva

Thmar

@ DRIVER
DATA

Tsuskew: flight time skew for setup Tsumar: setup margin Tvb: min driver phase offset (setup)
H. Heck 2008

Thskew: flight time skew for hold Thmar: hold margin Tva: min driver phase offset (hold)
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Source Synchronous Equations

@ RECEIVER
STROBE/STROBE

Tsumar Tsuskew Tvb

Tsu Th Thskew Tva

Thmar

Source Synchronous Timing

@ DRIVER
DATA

The sum of the timings at the receiver must not exceed the phase offsets at the driver: Tvb = Tsu + Tsuskew + Tsumar [4.3.1] Tva = Th + Thskew + Thmar [4.3.2] the transmitter design requires minimum offsets:

Tvb Tsu + Tsuskew

H. Heck 2008

[4.3.3]

Tva Th + Thskew

[4.3.4]
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Source Synchronous Equations #2

@ RECEIVER
STROBE/STROBE

Tsumar Tsuskew Tvb

Tsu Th Thskew Tva

Thmar

Source Synchronous Timing

@ DRIVER
DATA

We must also satisfy the following relationship: Tbit ,min Tva + Tvb [4.3.5] Tbit: data bit width This determines our maximum transfer rate. TRmax = 1 TRmax: max transfer rate Tbit ,min [4.3.6]
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Question

Based on what weve covered in the previous slides, what are the implications to:
The transmitter design? The receiver design? The interconnect design?

Source Synchronous Timing

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Example Tsu = 500 ps, Th = 500 ps The target transfer rate is 500 MT/s. What are reasonable flight time skew targets? SETUP HOLD
x ns x ns 1.0 ns

Source Synchronous Timing

CLK/CLK# @ Tx DATA @ Tx

1.0 ns

x - 0.5 ns

x + 0.5 ns

DATA @ Rx CLK/CLK# @ Rx
H. Heck 2008
Tsu = 0.5 ns Th = 0.5 ns

Section 4.3

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Source Synchronous Timing Summary

Synchronous timings are limited by absolute delays. Source synchronous timings use a strobe eliminate dependence on absolute delay.
Performance depends on our ability to maintain known phase relationship between data & strobe

Source Synchronous Timing

As a result, source synchronous interfaces typically operate at 2x-8x the clock frequency.
Expect that ratio to scale much higher in the future.

Matching of delays (transmitter & interconnect) is a key design consideration for designing high speed source synchronous interfaces.

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Section 4.3

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References
S. Hall, G. Hall, and J. McCall, High Speed Digital System Design, John Wiley & Sons, Inc. (Wiley Interscience), 2000, 1st edition. W. Dally and J. Poulton, Digital Systems Engineering, Cambridge University Press, 1998. R. Poon, Computer Circuits Electrical Design, Prentice Hall, 1st edition, 1995. H.B.Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison Wesley, 1990. H. Johnson and M. Graham, High Speed Digital Design: A Handbook of Black Magic, PTR Prentice Hall, 1993. S. Dabral and T. Maloney, Basic ESD and I/O Design, John Wiley and Sons, New York, 1998.
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Source Synchronous Timing

Source Synchronous Timing

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Appendix: Source Synchronous Timing Equation Derivation

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Source Synchronous Bus Operation

Driver Chip
From Core

DELAY

Strobe n

Source Synchronous Timing

From Core

P L L Clock Distribution Tree

Data

Receiver Chip

Data Q D Q D

To Core

System Clock Strobe P L L Clock Distribution Tree

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Operation #2
The timing path starts at the flip-flop of the transmitting agent and ends at the flip-flop of the receiving agent. The strobe signal is used as the clock input of the receiver flip-flop.

Driver Chip

From Core

DELAY

D Q Strobe n

n
From Core

D Q Data

P L L Clock Distribution Tree

Source Synchronous Timing

Receiver Chip Core To

System Clock

Data Q D Q D n

P L L Clock Distribution Tree

The transmitted strobe (and data) signals are generated from the on-chip bus clock. Typically, the strobe is phase shifted by cycle from the data signal.
Duty cycle variations will cause variation on the phase relationship
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Strobe

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Setup Timing Diagram & Loop Analysis

TBCLK

BCLK
TBCLK /4

DCLK

Source Synchronous Timing

Tco(STB)

DRIVER STB/STB
Tco(DATA) Tflight(STB)

DRIVER

DATA

RECEIVER STB/STB
Tflight(DATA) Tsu

RECEIVER

DATA

Tsumar

TBCLK

+ Tco ( STB ) + T flight ( STB ) Tsu Tsumar Tco ( DATA) T flight ( DATA) = 0
Section 4.3

[4.3.1a]
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Setup Analysis
TBCLK 4 + Tco ( STB ) + T flight ( STB ) Tsu Tsumar Tco ( DATA) T flight ( DATA) = 0
[4.3.1a]

Source Synchronous Timing

For a double pumped bus, the difference between Tco(DATA) and Tco(STB) is typically set to one-half of the cycle time (TDCLK/2 = TBCLK/4) to center the strobe in the data valid window.
Double pumped: source synchronous transfer rate is 2x the central clock rate.

This relationship is typically specified as Tvb (data valid before strobe ), which signifies the minimum time for which the data at the transmitter is valid prior to transmission of the strobe. Mathematically: T [4.3.2a] Tvb,min [Tco ( DATA) Tco ( STB ) ] max BCLK 4 Simplify the loop equation:

Tvb ,min + T flight ( STB ) Tsu Tsumar T flight ( DATA) = 0

H. Heck 2008 Section 4.3

[4.3.3a]
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Setup Analysis #2
Tvb ,min = Tsu + T flight ( STB ) T flight ( DATA) Tsumar
[4.3.4a]

Both data & strobe propagate over the interconnect.

Goal: identical flight times.

Source Synchronous Timing

In reality, there will be some difference in flight times between data and strobe.
trace length, loading, crosstalk, ISI, etc.

Define flight time skew for the setup condition:

[4.3.5a]

Simplify the loop equation:

Tvb ,min = Tsu Tsuskew Tsumar
[4.3.6a]

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Notes on the Setup Equation

Tvb ,min = Tsu + Tsuskew + Tsumar
You may see the timing equation written in other forms. The way I defined Tvb makes it a negative quantity. Others may define it to be positive. I defined Tsuskew to be a positive quantity.
[4.3.7a]

Source Synchronous Timing

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Hold Timing Diagram & Loop Analysis

TBCLK

BCLK
TBCLK/4

Source Synchronous Timing

DCLK
Tco(STB) Tco(DATA)

DRIVER STB/STB
Tflight(STB)

DRIVER

DATA

RECEIVER STB/STB

Tflight(DATA)

Th
Thmar

RECEIVER

DATA

t TBCLK 4 + Tco ( DATA) + T flight ( DATA) Thmar Thold T flight ( STB ) Tco ( STB ) = 0
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Hold Analysis
TBCLK 4 + Tco ( DATA) + T flight ( DATA) Thmar Thold T flight ( STB ) Tco ( STB ) = 0
[4.3.8a]

Source Synchronous Timing

Just as for the setup case, we need to specify the minimum phase relationship between data and strobe:
Tva ,min [Tco ( DATA) Tco ( STB ) ] min + TBCLK 4

[4.3.9a]

In addition, define the flight time skew for the hold case: Thskew [T flight ( DATA) T flight ( STB ) ] min [4.3.10a] In addition, define the flight time skew for the hold case: Tva ,min = +Thold Thskew + Thmar [4.3.11a] Note that the Thskew is defined such that it is a negative quantity, while Tva is defined to be positive. Section 4.3 H. Heck 2008

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Maximum Transfer Rate

-Tvb,min
STB/STB DATA

Tva,min

Source Synchronous Timing

Tcycle,min

The maximum transfer rate can be determined using the definitions for Tva and Tvb.
TBCLK = 4(Tva ,min [Tco ( DATA) Tco ( STB ) ] min ) TBCLK = 4( Tvb,min + [Tco ( DATA) Tco ( STB ) ] max )

s We can calculate the limit of TBCLK (for a double pumped bus) by adding the two equations above.
TBCLK ,min = 4( Tvb,min + Tva ,min )
H. Heck 2008 Section 4.3

[4.3.12a]
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Higher Transfer Rates (e.g. Quad Pumped)

TBCLK TBCLK

BCLK
TBCLK/8

BCLK TBCLK/8 DCLK Tco(STB) DRIVER STB/STB Tflight(STB) DRIVER DATA Thold Tmargin RECEIVER DATA Tco(DATA)

DCLK Tco(STB) DRIVER STB/STB Tflight(STB)

Source Synchronous Timing

Tco(DATA) DRIVER DATA

RECEIVER STB/STB Tflight(DATA) RECEIVER DATA

Tmargin

Tsetup

RECEIVER STB/STB Tflight(DATA)

The setup and hold equations remain the same. What changes are the Tva and Tvb definitions:
Tvb [Tco ( DATA) Tco ( STB ) ] max Tva [Tco ( DATA) Tco ( STB ) ] min +
H. Heck 2008 Section 4.3

TBCLK TBCLK

8 8

[4.3.13a] [4.3.14a]
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