WEEK-5: 8086 hardware details, Pins &

Signals, Minimum versus Maximum

mode operation, Bus buffering and
latching (2 Lectures)
 Standard TTL Output and Input Voltage Levels
Vcc 5.0 V
11Logic
LogicLevel
Level

“1”-Level
Noise Margin
Guaranteed Forbidden Accepted
Output Levels Forbidden
Region Input Levels

“0”-Level
0 Logic Level Noise Margin
• 8086 can work in two
modes: Minimum
mode and Maximum
mode
• Pins-33 is used to
select mode
• 20-bit address bus & 16 bit
data bus
• Does not have separate
address and data bus
• Multiplexed bus system
• Pins 24 – 31 have different
functions in two modes
 Pin-33: Input pin
to select Min/ Max

The 8086 microprocessor can work in two

modes of operations : Minimum mode and
Maximum mode.

In the minimum mode of operation the

microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.

In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.

Minimum or maximum mode operations

are decided by the pin MN/ MX(Active
low).

When pin-33 is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.

5
 +5V

33 33

GND

8086: minimum 8086: maximum

mode mode

• MN/MX input: Selects either

• Minimum (+ 5V directly)
• or Maximum mode (GND)
8086 Microprocessor
Pins and Signals Common signals

AD0-AD15 (Bidirectional)

Address/Data bus

Low order address bus; these are

multiplexed with data.

When AD lines are used to transmit

memory address the symbol A is used
instead of AD, for example A0-A15.

When data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

multiplexed with status signals

7
Bus Demultiplexing

The address/data and

address/status buses
are multiplexed to
reduce the device pin
count. These buses
must be demultiplexed
(separated) to obtain
the signals required for
interfacing other
circuits to the P
Bus Demultiplexing and
Buffering
• Demultiplexing:
The address/data and address/status buses
are multiplexed to reduce the device pin
count. These buses must be demultiplexed
(separated) to obtain the signals required
for interfacing other circuits to the P
– Use the ALE output from the microprocessor to
latch the address/status information that appear
briefly on the multiplexed bus
– This makes the latched address information
available for long enough time for correct
interfacing, e.g. to memory
• Buffering:
Fan out is limited, so output signals should
be buffered in large systems
 ALE

A19
AD15 ADDRESS BUS

AD0

DATA BUS

8086
• ALE (address latch enable) output: Controls latches.
• 8086 uses ALE to latch the address/status information
that appear briefly on the multiplexed bus. Thus ALE is
used to demultiplex address and data bus.
• This makes the latched address information available
for long enough time for correct interfacing, e.g. to
memory
Bus Buffering
Fan-out is a term that defines the maximum number
of digital inputs that the output of a single logic gate
can feed.
Most transistor-transistor logic ( TTL ) gates can feed
up to 10 other digital gates or devices. Thus, a
typical TTL gate has a fan-out of 10.
Buffering is often needed if more TTL loads are
connected to any bus signal.
Buffering introduces a small delay in the buffered
signals. This is acceptable unless memory or I/O
devices operate close to the maximum bus speed
For demuxed signals: Latches used for demuxing, e.g.
74LS373, can also provide the buffering for the
demuxed lines.
For non-demuxed bidirectional data signals (pin used
for both in and out), buffering is often accomplished
with the 74ALS245 bidirectional bus buffer
 ALE

A19
AD15 ADDRESS BUS

AD0
BUS
BUS Trans-
Trans- receiver
DATA BUS
receiver

DEN

DT/R

• (Data Transmit/ Receive) Output signal from the

processor to control the direction of data flow through
the data transceivers
• (Data Enable) Output signal from the processor used
as output enable for the transceivers
 ALE

A19 ADDRESS BUS

AD15
BUS
AD0 BUS Trans-
DATA BUS Trans- receiver
receiver

DEN
DT/R

• DT/R output: Use to control external bidirectional

buffers connected to the data bus.
– During write operation, microprocessor places ‘1’ on this pin

– During read operation, microprocessor places ‘0’ on this pin

• DEN output: (data bus enable). Microprocessor

places ‘0’ on this pin to activate buffers
13
 FFFFEH LOWER ADDRESS FFFFFH HIGHER ADDRESS
BANK BANK
512KB 512KB
ONLY EVEN ONLY ODD
A0 ADDRESSES ADDRESSES

00001H
00000H
BHE

D7 - D0 D15 - D8

• BHE (Bus High Enable) and A0 are used to

select Memory banks
• A0: Lower address bank
• BHE: Higher address bank
RD output indicates
a read operation
WR output indicates
a write operation
READY input: when
low forces the
processor to enter
a wait state.
Facilitates
interfacing the
processor to slow
memory chips
• INTR input: Interrupt Request
• INTA output: interrupt acknowledgement.
• These two pins are used to manage External Maskable
Hardware Interrupts
• 8086 receives interrupt request at INTR input pin from
external source.
Then 8086 checks Interrupt Flag(IF) bit. If IF is found ‘1’,
8086 sends acknowledgement to requesting device through
INTA output pin.

INTR
Input
8086 Device
INTA
• To increase number of devices to be served in
interrupt mode, 8259 IC is used with 8086 and INTR
& INTA pins are used to interface between these.
• To enable IF flag bit, STI instruction is used
• To clear IF flag bit, CLI instruction is used
NMI input: Hardware non-maskable interrupt request.
Served regardless of the status of the IF flag bit.
Application: To detect power failure in small system
To detect parity error while reading data from memory
 Test for low

8087
8086
Math
processor TEST Busy Coprocessor
O/P
Synchronizes
processor execution to external events
• TEST input:
• Example: interfacing 8086 with the 8087
math coprocessor. Checked by the WAIT
instruction that precedes each floating point
(FP) instruction. If high, the instruction waits
till input signal goes low and then gives FP
instruction to the math processor
 8086
Main Memory

HOLD DMA controller Controller

HLDA

storage/
devices

• HOLD input & HLDA output pins are used to

interface 8086 with Direct Memory Access (DMA)
controller to implement Direct Memory Access
operation.
• 8086 receives request from DMA controller at HOLD
input pin and if accepted, acknowledgement is sent
to DMA controller through HLDA output pin.
 8086
Main Memory

HOLD DMA controller Controller

HLDA
storage/
devices

• HOLD input: Input signal to the processor form the bus masters as a
request to grant the control of the bus. Usually used by the DMA
controller to get the control of the bus. In response, the P stops
execution and places the data, address, and control buses at High Z
state (floats them).
• HLDA output: Acknowledge signal by the processor to the bus
master requesting the control of the bus through HOLD. The
acknowledge is asserted high, when the processor accepts HOLD.
• Acknowledges that the processor has entered a hold state in response to
HOLD.
 2.5 MHz
PCLK

Manual Reset
push button
Switch

The clock input provides the basic timing for

processor operation and bus control activity.
Its an asymmetric square wave with 33%
duty cycle.
For 10-MHz 8086
CPU clock cycle has a period of
100ns
Fast rise and fall times ( <10ns )

33% Duty Cycle

Logic 0: -0.5 to 0.6 V
Logic 1: 3.9 to 5.0 V
• RESET input: resets the microprocessor or
reboot the computer.
• Clears all CUP registers except CS register

• CS register is set to FFFFH

• Causes the processor to start executing at

address FFFF0H, since IP = 0000H.
• RESET Input must be kept high for at least 4
clock cycles.
8086 Microprocessor
Pins and Signals Common signals

READY

This is the acknowledgement from the

slow device or memory that they have
completed the data transfer.

The signal made available by the devices

is synchronized by the 8284A clock
generator to provide ready input to the
8086.

The signal is active high. 25

8086 Microprocessor
Pins and Signals Maximum mode signals

26
8086 Microprocessor
Pins and Signals Maximum mode signals

27
8086 Microprocessor
Pins and Signals Maximum mode signals

28
• S0,S1,S2 outputs: Used
to interface 8288 bus
controller with 8086
33
running in maximum
mode S2
28
8 S1
0 27
8288
8 26
S0

S0,S1,S2 outputs: Status bits that encode

the type of the current bus cycle, Used
by the 8288 bus controller and the 8087
coprocessor
 The Clock (10 MHZ signal)

• The clock signal is very important

to the operation of a
microprocessor
• It synchronizes the sequential
activities of the CPU and the
system
• 8086 does not have internal clock
generator
• 8086 requires an external clock
generator IC
• Clock signal is applied to Pin # 19
 Clock Generator (8284A)

Generates a CLK signal for the 8086/8088

Provides synchronization for external input
signals to the processor:
The RESET input
The READY input for wait state generation
 Machine Cycles/Bus Cycles
• One discrete information transfer on the buses.
• This includes the address, data, and control information.
• A machine (bus) cycle consists of at least four clock cycles,
called T states.
• A specific, defined action occurs during each T state (labeled T1
– T4)
– T1: Address is output
– T2: Bus cycle type (Mem/IO, read/write)
– T3: Data is supplied
– T4: Data latched by CPU, control signals removed
 Bus Timing
Timing in General
• A data transfer operation to/from
Clock Cycle
the P occupies at least one
bus cycle
• Each bus cycle consists of
4 clock cycles, T1, T2, T3, T4,
each of period T
• With 5 MHz processor clock:

- T = 1/5 MHz = 0.2 s

- Bus cycle = 4 T = 0.8 s
- Max rate for memory and I/O
transactions = 1/0.8 = 1.25 M
operations per sec (Fetch speed).
- Processor executes
2.5 Million Instructions per sec
(MIPS) (Execute speed)  Fetch is slower than execute. Effect on pipelining?
 Clock Generator (8284A)
Provides the following functions:
• Generates Clock signals:
- Generates a CLK signal for the 8086/8088
- Provides a CLK sync signal (OSC) for use by slave
processors on a multiprocessor 8086/8088
systems
- Provides a TTL-level peripheral clock signal
(PCLK)
• Provides synchronization for external
input signals to the processor:
– The RESET input
– The READY input for wait state generation
 Bus Demultiplexing and Buffering
Address & Data Buses
• For both : Address bus signals are A0-A19 (20 lines)
for 1M byte of addressing space
• Data bus signals are
- D0-D7
- D0-D15
• The address & data pins are multiplexed as:
- AD0-AD7
- AD0-AD15
• Address/Status pins are MUXed
- A/S for A16-19 (both Ps)
• The ALE signal is used to demultiplex the address/data
bus and the address/status bus.
 Bus Demultiplexing and Buffering
• Demultiplexing:
The address/data and address/status buses are
multiplexed to reduce the device pin count. These
buses must be demultiplexed (separated) to obtain the
signals required for interfacing other circuits to the P
– Use the ALE output from the microprocessor to latch the
address/status information that appear briefly on the
multiplexed bus
– This makes the latched address information available for
long enough time for correct interfacing, e.g. to memory
• Buffering:
Fan out is limited, so output signals should be buffered
in large systems
 Supporting Chips
74LS373 Latch
• Provide isolation and bus boosting

74LS244 Unidirectional data transceiver chip

74LS245 Bidirectional data transceiver chip

• Provide bus buffering and boosting
 20-bit

16-bit

with
#DEN active
Fully DeMuxed and buffered 8086
 Minimum and Maximum Modes
• MN/#MX input on 8088/8086 selects min (0V) or max (+V) mode
• Minimum mode is the least expensive way to configure a 8086/8088 system:
– Bus control signals are generated directly by processor
– Good backward compatibility with earlier 8085A 8 bit processor
- Same control signals
- Support same peripherals
• Maximum mode provides greater versatility at higher cost.
– New control signals introduced to support 8087 coprocessor (e.g. QS0 &QS1) and
multiprocessor operation (e.g. #RQ/GT0 & RQ/GT1)
– Control signals omitted must be externally generated using an external bus
controller, e.g. 8288. The controller decodes those control signals from the
now compressed form of 3 control bits (#S0,#S1,#S2)
– Can be used with the 8087 math coprocessor
– Can be used with multiprocessor systems
• Maximum mode no longer supported since 80286
System design using 8086 in minimum mode
System design using 8086 in minimum mode
Use of 8086 in the Minimum Mode

Basic control signals are directly available from processor

Address
Demultiplexing

Address
Decoding
Direction
Bidirectional
AD Bus Data Buffering

RAM ROM I/O

Interrupt
Handling Several Interrupt
Requests
 8288 Bus Controller

bus
20-Pin Chip

Familiar 8088/8086
Outputs
More specific Outputs,
Selects Replace #RD, #WR,
Mode: M/#IO
1. I/O Bus
2. System Bus
8086 Maximum Mode
8288 Bus Controller chip: Necessary in this mode.
Generates essential control signals not provided directly by P
form the S0-S2 O/Ps

Control signals are more specific, e.g. separate lines for

M and I/O operations
 questions
• Briefly explain the functions of the following pairs of pins and signals of 8086
– BHE and A0
– HOLD and HLDA
– ALE
– INTR and INTA
– DEN and DT/R
– CLK & RESET
– MN/MX
• Draw a simplified diagram of a system (personal computer) based on 8086 running in the
maximum mode, briefly describe.
• Explain, why buffers are needed in designing system based on 8086?
• What do you understand by multiplexed bus system, state its merits and demerits.
• What do you understand by fully demultiplexed fully buffered system?
• For 8086, show how byte addressable 1MB memory is interfaced with 16 bit data bus, address
bus and control signals.
• Draw a simplified diagram of a system (personal computer) based on 8086 running in the
minimum mode, briefly describe.
• What are IC 8288 and IC 8284? Why these are used in 8086 based system design?