Lec5 8051 Architecture
Lec5 8051 Architecture
Architecture
2. Half duplex communication link: In half duplex, the communication link can be used for either transmission or
reception. Data is transmitted in only one direction at a time.
SERIAL COMMUNICATION
3. Full duplex communication link: If the data is transmitted in both ways at the same time, it is a full duplex i.e. transmission and
reception can proceed simultaneously. This communication link requires two wires for data, one for transmission and one for
reception.
Baud rate:
The rate at which the data is transmitted is called baud or transfer rate. The baud rate is the reciprocal of the time
to send one bit. In asynchronous transmission, baud rate is not equal to number of bits per second. This is
because; each byte is preceded by a start bit and followed by parity and stop bit. For example, in synchronous
transmission, if data is transmitted with 9600 baud, it means that 9600 bits are transmitted in one second. For bit
transmission time = 1 second/ 9600 = 0.104 ms.
SERIAL COMMUNICATION
1. SBUF Register: Serial Buffer (SBUF) register is an 8-bit register. It has separate SBUF registers for data
transmission and for data reception. For a byte of data to be transferred via the TXD line, it must be placed in
SBUF register(Write only). Similarly, SBUF holds the 8-bit data received by the RXD pin and read to accept the
2. SCON register: The contents of the Serial Control (SCON) register are shown below. This register contains
mode selection bits, serial port interrupt bit (TI and RI) and also the ninth data bit for transmission and
Where,
• SMOD is the 7th bit of PCON register
• fosc is the crystal oscillator frequency of the microcontroller
• It can be noted that fosc/ (12 X [256- (TH1)]) is the timer overflow
frequency in timer mode-2, which is the auto-reload mode.
SERIAL COMMUNICATION MODES
If timer-1 is not run in mode-2, then the baud rate is,
Timer-1 can be run using the internal clock, fosc/12 (timer mode) or
from any external source via pin T1 (P3.5) (Counter mode).
SERIAL COMMUNICATION MODES
Example: If standard baud rate is desired, then 11.0592 MHz crystal could be selected.
• To get a standard 9600 baud rate, the setting of TH1 is calculated as follows.
• Assuming SMOD to be '0'
Or
Or
In mode-1, if SM2 is set to 1, no receive interrupt (RI) is generated unless a valid stop
bit is received.
Serial Data Mode-2 - Multiprocessor Mode :
• 8051 operates in multiprocessor mode for serial communication Mode-2 and Mode-3. In
multiprocessor mode, a Master processor can communicate with more than one slave
processors. The connection diagram of processors communicating in Multiprocessor is below
• The Master communicates with one slave at a time. 11 bits are transmitted by the Master,
viz, One start bit (usually '0'), 8 data bits (LSB first), TB8 and a stop bit (usually '1'). TB8 is '1'
for an address byte and '0' for a data byte.
• If the Master wants to communicate with certain slave, it first sends the address of the slave
with TB8=1. This address is received by all the slaves. Slaves initially have their SM2 bit set
to '1'. All slaves check this address and the slave who is being addressed, responds by
clearing its SM2 bit to '0' so that the data bytes can be received.
• It should be noted that in Mode 2&3, receive interrupt flag RI is set if REN=1, RI=0 and the
following condition is true.
• SM2=1 and RB8=1 and a valid stop bit is received. Or
• SM2=0 and a valid stop bit is received.
• After the communication between the Master and a slave has been established, the data
bytes are sent by the Master with TB8=0. Hence other slaves do not respond /get
interrupted by this data as their SM2 is pulled high (1).
Operation in Multiprocessor mode
SERIAL COMMUNICATION
CONNECTIONS TO RS-232
RS-232 standards:
To allow compatibility among data communication equipment made by various manufactures, an interfacing
standard called RS232 was set by the Electronics Industries Association (EIA) in 1960. Since the standard was set
long before the advent of logic family, its input and output voltage levels are not TTL compatible.
In RS232, a logic one (1) is represented by -3 to -25V and referred as MARK while logic zero (0) is represented by
+3 to +25V and referred as SPACE. For this reason to connect any RS232 to a microcontroller system we must use
voltage converters such as MAX232 to convert the TTL logic level to RS232 voltage levels and vice-versa. MAX232
IC chips are commonly referred as line drivers.
In RS232 standard we use two types of connectors. DB9 connector or DB25 connector.
SERIAL COMMUNICATION
The 8051 connection to MAX232 is as follows.
The 8051 has two pins that are used specifically for transferring and receiving data serially. These two pins are
called TXD, RXD. Pin 11 of the 8051 (P3.1) assigned to TXD and pin 10 (P3.0) is designated as RXD. These pins TTL
compatible; therefore they require line driver (MAX 232) to make them RS232 compatible. MAX 232 converts
RS232 voltage levels to TTL voltage levels and vice versa. One advantage of the MAX232 is that it uses a +5V power
source which is the same as the source voltage for the 8051. The typical connection diagram between MAX 232 and
8051 is shown below.
Power saving modes of operation
The schematic diagram for 'Power down' mode and 'Idle' mode is given
as follows:
Power saving modes of operation
• Idle Mode
Idle mode is entered by setting IDL bit to 1 (i.e.,IDL =0). The clock signal is
gated off to CPU, but not to the interrupt, timer and serial port functions. The
CPU status is preserved entirely. SP, PC, PSW, Accumulator and other registers
maintain their data during IDLE mode. The port pins hold their logical states they
had at the time Idle was initiated. ALE and PSEN are held at logic high levels.
Ways to exit Idle Mode:
• Activation of any enabled interrupt will clear PCON.0 bit and hence the Idle
Mode is exited. The program goes to the Interrupt Service Routine (ISR). After
RETI is executed at the end of the ISR, the next instruction will start from the
one following the instruction that enabled Idle Mode.
• A hardware reset exits the idle mode. The CPU starts from the instruction
following the instruction that invoked the 'Idle' mode.
Power saving modes of operation