Chapter #5: MOSFET’s

from Microelectronic Circuits Text

by Sedra and Smith
Oxford Publishing

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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 Introduction

 IN THIS CHAPTER WE WILL LEARN

 The physical structure of the MOS transistor and how
it works.
 How the voltage between two terminals of the
transistor control the current that flows through the
third terminal, and the equations that describe these
current-voltage characteristics.
 How the transistor can be used to make an amplifier,
and how it can be used as a switch in digital circuits.
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 Introduction

 IN THIS CHAPTER WE WILL LEARN

 How to obtain linear amplification from the
fundamentally nonlinear MOS transistor.
 The three basic ways for connecting a MOSFET to
construct amplifiers with different properties.
 Practical circuits for MOS-transistor amplifiers that
can be constructed using discrete components.

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 Introduction

 We have studied two-terminal semi-conductor devices

(e.g. diode).
 However, now we turn our attention to three-terminal
devices.
 They are more useful because they present multitude of
applications, e.g:
 signal amplification, digital logic, memory, etc…

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 Introduction

 Q: What, in simplest terms, is the

desired operation of a three-terminal
device?
 A: Employ voltage between two
terminals to control current flowing
in to the third.

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 note: MOSFET is more widely used in
Introduction implementation of modern electronic
devices

 Q: What are two major types of  MOSFET technology

three-terminal semiconductor  It allows placement of
devices? approximately 2 billion
 metal-oxide-semiconductor transistors on a single IC
field-effect transistor (MOSFET)  backbone of very large scale
 bipolar junction transistor (BJT) integration (VLSI)
 Q: Why are MOSFET’s more widely  It is considered preferable to
used? BJT technology for many
 size (smaller) applications.
 ease of manufacture
 lesser power utilization

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 5.1. Device Structure
and Operation

 Figure 5.1. shows general structure of the n-channel

enhancement-type MOSFET

Figure 5.1: Physical structure of the enhancement-type NMOS transistor: (a) perspective view, (b) cross-
section. Note that typically L = 0.03um to 1um, W = 0.1um to 100um, and the thickness of the oxide
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layer
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ox) is in the range of 1 to 10nm.
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 two n-type doped
5.1. Device Structure regions (drain, source)
and Operation
layer of SiO2 separates
source and drain

metal, placed on top of

SiO2, forms gate
electrode

one p-type doped region

Figure 5.1: Physical structure of the enhancement-type NMOS transistor: (a) perspective view, (b) cross-
section. Note that typically L = 0.03um to 1um, W = 0.1um to 100um, and the thickness of the oxide
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layer
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ox) is in the range of 1 to 10nm.
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 5.1. Device Structure
and Operation

 The name MOSFET is derived  The device is composed of

from its physical structure. two pn-junctions, however
 However, many MOSFET’s do they maintain reverse biasing
not actually use any “metal”, at all times.
polysilicon is used instead.  Drain will always be at
 “This” has no effect on positive voltage with
modeling / operation as respect to source.
described here.  We will not consider
 Another name for MOSFET is conduction of current in this
insulated gate FET, or IGFET. manner.
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 5.1.2. Operation with
Zero Gate Voltage

 With zero voltage applied to

gate, two back-to-back diodes
exist in series between drain
and source.
 “They” prevent current
conduction from drain to
source when a voltage vDS is
applied.
 yielding very high
resistance (1012ohms)
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Figure 5.1: Physical structure…
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 5.1.3. Creating a
Channel for
Current Flow

 Q: What happens if (1) source and

drain are grounded and (2) positive
voltage is applied to gate? Refer to
figure to right.
 step #1: vGS is applied to the
gate terminal, causing a positive
build up of positive charge along
metal electrode.
 step #2: This “build up” causes
free holes to be repelled from
region of p-type substrate under
gate. Figure 5.2: The enhancement-type NMOS transistor
with a positive voltage applied to the gate. An n
channel is induced at the top of the substrate
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 Q: What happens if (1) source
and drain are grounded and (2)
positive voltage is applied to
gate? Refer to figure to right.

 step #3: This “migration”

results in the uncovering of
negative bound charges,
originally neutralized by the
free holes
 step #4: The positive gate
voltage also attracts electrons
from the n+ source and drain
regions into the channel.
Figure 5.2: The enhancement-type NMOS transistor
with a positive voltage applied to the gate. An n
channel is induced at the top of the substrate
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 Q: What happens if (1) source this induced channel is
and drain are grounded and (2) also known as an
positive voltage is applied to inversion layer
gate? Refer to figure to right.

 step #5: Once a sufficient

number of “these” electrons
accumulate, an n-region is
created…
 …connecting the source
and drain regions
 step #6: This provides path for
current flow between D and S.

Figure 5.2: The enhancement-type NMOS transistor

with a positive voltage applied to the gate. An n
channel is induced at the top of the substrate
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 5.1.3. Creating a Vtn is used for n-type
MOSFET, Vtp is used for
Channel for
p-channel
Current Flow

 threshold voltage (Vt) – is the  effective / overdrive voltage – is

minimum value of vGS required to the difference between vGS applied
form a conducting channel between and Vt.
drain and source (eq5.1) vOV  vGS  Vt
 typically between 0.3 and 0.6Vdc
 field-effect – when positive vGS is
applied, an electric field develops  oxide capacitance (Cox) – is the
between the gate electrode and capacitance of the parallel plate
induced n-channel – the capacitor per unit gate area (F/m2)
 ox is permittivity of SiO2 3.45E11F / m 
conductivity of this channel is
affected by the strength of field
tox is thickness
  of SiO
 2 layer   
 ox
 SiO2 layer acts as dielectric (eq5.3) C ox  in F / m2
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tox
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 5.1.3. Creating a
Channel for
Current Flow

 Q: What is main requirement for n-  Q: How can one express the

channel to form? magnitude of electron charge
 A: The voltage across the contained in the channel?
“oxide” layer must exceed Vt.  A: See below…
 For example, when vDS = 0… W and L represent width and length of channel respectively
           
 the voltage at every point along (eq5.2) Q  C ox WL vOV in C
channel is zero
 the voltage across the oxide  Q: What is effect of vOV on n-
layer is uniform and equal to vGS channel?
 A: As vOV grows, so does the
depth of the n-channel as well
as its conductivity.
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 5.1.4. Applying a
Small vDS

 Q: For small values of vDS, how does one calculate iDS

(aka. iD)? A: Equation (5.7)…
 Q: What is the origin of this equation?
 A: Current is defined in terms of charge per unit
length of n-channel as well as electron drift velocity.
n represents mobility of electrons at surface of the
n-channel in m2 / Vs
            
 nvDS 
(eq5.7) iD  C oxWvOV  in A
      L 
charge per unit   
length of electron
n -channel drift velocity
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in C / m
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 5.1.4. Applying
a Small vDS

 Q: How does one calculate charge per unit length of n-

channel (Q/uL)?
 A: For small values of vDS, one can still assume that
voltage between gate and n-channel is constant
(along its length) – and equal to vGS.
 A: Therefore, effective voltage between gate and n-
channel remains equal to vOV.
 A: Therefore, (5.2) from two slides back applies.
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 5.1.4. Applying a
Small vDS

action: divide both sides by L

 Q: How does one calculate       
charge per unit length of n- (eq5.2) Q  C ox WL vOV in C
channel (Q/uL)? Q
 A: Use (5.2) to calculate (eq5.4)  C oxWvOV in C / m
L
charge per unit L of channel.
 Q: How does one calculate vDS
electron drift velocity? (eq5.5) E  in V / m
L
 A: Note that vDS establishes (eq5.6) e-drift velocity  
an electric field E across
length of n-channel, this may V m2 m
  n E in 
calculate e-drift velocity. m Vs s
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 5.1.4. Applying a
Small vDS

action: divide both sides by L

 Q: How does one calculate       
charge per unit length of n- (eq5.2) Q  C ox WL vOV in C
channel (Q/uL)? Q
Note that these two
 A: Use (5.2) to calculate (eq5.4)  C oxWvOV in C / m
values mayperbeunit
employed L
charge L of channel.
 toQ:define current
How does in
one calculate vDS
amperes (aka.velocity?
electron drift C/s). (eq5.5) E  in V / m
L
 A: Note that vDS establishes (eq5.6) e-drift velocity  
an electric field E across
length of n-channel, this may V m2 m
  n E in 
calculate e-drift velocity. m Vs s
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 5.1.4. Applying a
Small vDS

 Q: What is observed from equation (5.7)?

 A: For small values of vDS, the n-channel acts like a
variable resistance whose value is controlled by vOV.

 W 
(eq5.7) iD   nC ox  vOV  vDS in A
 L 
vDS 1
(eq5.8a) rDS   in 
iD W 
nCox    vOV

 L 
process
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transconductance aspect
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033) parameter ratio
 5.1.4. Applying a Note that this vOV represents
the depth of the n-channel -
Small vDS what if it is not assumed to
be constant? How does this
equation change?
Note
Q: that
Whatthisdo
is we
one note
VERY from equation (5.7)?
IMPORTANT equation
 A: For small in of v , the n-channel acts like a
values DS
Chapter 5.
variable resistance whose value is controlled by vOV.

 W 
(eq5.7) iD   nC ox  vOV  vDS in A
 L 
vDS 1
(eq5.8a) rDS   in 
iD W 
nCox    vOV

 L 
process
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transconductance aspect
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033) parameter ratio
 5.1.4. Applying a
Small vDS

 Q: What three factors is rDS dependent on?

 A: process transconductance parameter for NMOS
(nCox) – which is determined by the manufacturing
process
 A: aspect ratio (W/L) – which is dependent on size
requirements / allocations
 A: overdrive voltage (vOV) – which is applied by the
user
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 kn is known as NMOS-FET
transconductance parameter
and is defined as nCoxW/L

1/rDS

low resistance, high vOV

high resistance, low vOV

Figure 5.4: The iD-vDS characteristics of the MOSFET in Figure 5.3.
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when the voltage applied between drain and source VDS is kept small.
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 5.1.5. Operation as
vDS is Increased

 Q: What happens to iD when vDS increases beyond “small values”?

 A: The relationship between them ceases to be linear.
 Q: How can this non-linearity be explained?
 step #1: Assume that vGS is held constant at value greater than
Vt.
 step #2: Also assume that vDS is applied and appears as voltage
drop across n-channel.
 step #3: Note that voltage decreases from vGS at the source end
of channel to vGD at drain end, where…
 vGD = vGS – vDS
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 v =V +v –v
 vOV vDS

The voltage differential

between both sides of n-
channel increases with vDS.

Figure 5.5: Operation of the e-NMOS transistor as vDS is increased.

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 note the average value note that we can define total
charge stored in channel |Q|
as area of this trapezoid

Q  vOV  12 vDS L

Figure 5.6(a): For a MOSFET with vGS = Vt + vOV application of vDS causes the voltage drop along the
channel to vary linearly, with an average value of vDS at the midpoint. Since vGD > Vt, the channel still
exists at the drainOxford end. (b) The
University channel shape corresponding to the situation in (a). While the depth of
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the channel at the source is still proportional to vOV, the drain end is not.
 Q: How can this non-
linearity be explained?

 vOV with vOV  12 vDS 

action: replace

      
W
 step #4: Define iDS (eq5.7) iD   nC ox  vOV  12 vDS  vDS
 L 
in terms of vDS and  
vOV.  W
   n C ox   v OV  2 vDS vDS
1
if vDS  vOV
iD is dependent on the L

(eq5.7) iD   W
apparent vOV (not vDS    n C ox   v OV  2 vDS vDS
1
otherwise
     L      
inherently) which does not  if vDS vOV then vDS vOV

change after vDS > vOV  W

   n C ox   v OV  2 vDS v DS
1
if vDS  vOV
(eq5.14) iD   L in A
 1 W

 nC ox  vO2 V otherwise
2 L
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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033) triode vs. saturation region
 saturation occurs
once vDS > vOV

 W
 triode:   n C ox   v OV  2 v DS v DS
1
if vDS  vOV
L
(eq5.14) iD   in A
 saturation: 1   C  W v 2 otherwise

n ox OV
2 L
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 pinch-off does not mean
5.1.6. Operation for blockage of current
vDS >> vOV

 In section 5.1.5, we assume

that n-channel is tapered but
channel pinch-off does not
occur.
 Trapezoid doesn’t become
triangle for vGD > Vt
 Q: What happens if vDS > vOV?
Figure 5.8: Operation of MOSFET with vGS = Vt +
 A: MOSFET enters vOV as vDS is increased to vOV. At the drain end,
saturation region. Any vGD decreases to Vt and the channel depth at
the drain-end reduces to zero (pinch-off). At
further increase in vDS has this point, the MOSFET enters saturation more
no effect on iD. Oxford University Publishing
of operation. Further increasing vDS (beyond
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
vOV) has no effect on the channel shape and iD
 Example 5.1: NMOS
MOSFET

 Example 5.1. Problem Statement: Consider an NMOS process

technology for which Lmin = 0.4m, tox = 8nm, n = 450cm2/Vs,
Vt = 0.7V.
 Q(a): Find Cox and k’n.
 Q(b): For a MOSFET with W/L = 8m/0.8m, calculate the
values of vOV, vGS, and vDSmin needed to operate the transistor in
the saturation region with dc current ID = 100A.
 Q(c): For the device in (b), find the values of vOV and vGS
required to cause the device to operate as a 1000ohm resistor
for very small vDS.
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 Quick Recap!

 The equation used n represents mobility of electrons at surface of the

n-channel in m2 / Vs
              
to define iD depends  nvDS 
(eq5.7) iD  C oxWvOV  in A
on relationship btw       L 
charge per unit   
vDS and vOV. length of
n -channel
electron
drift velocity
in C / m in m2 / Vs
 vDS << vOV
W
 vDS < vOV (eq5.14) iD   nC ox  vOV  12 vDS vDS in A
L
 vDS => vOV 1 W 2
(eq5.17) iD   nC ox  vOV in A
2 L
 vDS >> vOV 1 W 2
(eq5.23) i   n been

This Dhas not C ox  vOV 1  vyet!
covered DS  in A
2 L
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 5.2. Current-Voltage
Characteristics

 Figure 5.11. shows an n-

channel enhancement
MOSFET.
 There are four terminals:
 drain (D), gate (G), body
(B), and source (S).
 Although, it is assumed that
body and source are
connected.
Figure 5.11 (a): Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with
an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n
channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the effect
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 5.2. Current-Voltage
Characteristics

 Although MOSFET is symmetrical

device, one often designates
terminals as source and drain.
 Q: How does one make this the potential at drain (vD) is
designation? always positive with respect to
 A: By polarity of voltage applied. source (vS)
 Arrowheads designate “normal”
direction of current flow
 Note that, in part (b), we
designate current as DS.
 No need to place arrow with B.

Figure 5.11 (a): Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with
an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n
channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the effect
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 5.2.2. The iD-vDS
Characteristics

 Table 5.1. provides a

compilation of the
conditions and formulas
for operation of NMOS
transistor in three
regions.
 cutoff
 triode
 saturation
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 5.2.2. The iD-vDS
Characteristics

 At top of table, it shows circuit

consisting of NMOS transistor and
two dc supplies (vDS, vGS)
 This circuit is used to demonstrate
iD-vDS characteristic
 1st set vGS to desired constant
 2nd vary vDS
 Two curves are shown…
 vGS < Vtn
 vGS = Vtn + vOV

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Figure 5.12: The relative levels of the terminal voltages of the enhancement NMOS
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transistor
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Adel S. Sedra in(0195323033)
and Kenneth C. Smith the triode region and in the saturation region.
equation (5.14) as vGS increases, so do the (1) saturation current
and (2) beginning of the saturation region

Figure 5.13: The i – vPublishing

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DSKenneth C. Smith (0195323033)
for an enhancement-type NMOS transistor
 5.2.2. The iD-vGS
Characteristic

 Q: When MOSFET’s are employed to

design amplifier, in what range will
they be operated?
 A: saturation
 In saturation, the drain current (iD)
is…
 dependent on vGS
 independent of vDS
 In effect, it becomes a voltage-
controlled current source.
 This is key for amplification. Figure 5.13: The iD – vDS characteristics
for an enhancement-type NMOS
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  Q: What is one problem with (5.21)?
5.2.2. The iD-vGS  A: It is nonlinear w/ respect to
Characteristic vOV … however, this is not of
concern now.

 In effect, it becomes a voltage-

controlled current source.
 This is key for amplification.
 Refer to (5.21).
2
vOV
   
1 W 
(eq5.21) iD  kn   vGS  Vtn 
2

  2  L     
this relationship provides
basis for application of
MOSFET as amplifier

Figure 5.14: The iD-vGS characteristic of an NMOS transistor operating in the saturation region. The iD-vOV
characteristic can be obtained
Oxford by simply re-labeling the horizontal axis, that is, shifting the origin to the point
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vGS = Vtn.
 Example 5.2: NMOS
Transistor

 Example 5.2. Problem Statement: Consider an NMOS transistor

fabricated in an 0.18-m process with L = 0.18m and W = 2m.
The process technology is specified to have Cox = 8.6fF/m2, n =
450cm2/Vs, and Vtn = 0.5V.
 Q(a): Find VGS and VDS that result in the MOSFET operating at the
edge of saturation with ID = 100A.
 Q(b): If VGS is kept constant, find VDS that results in ID = 50A.
 Q(c): To investigate the use of the MOSFET as a linear amplifier, let
it be operating in saturation with VDS = 0.3V. Find the change in iD
resulting from vGS changing from 0.7V by +0.01V and -0.01V.
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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 5.2.4. Finite Output
Resistance in
Saturation

 In previous section, we assume (in saturation) iD is

independent of vDS.
 Therefore, a change vDS causes no change in iD.
 This implies that the incremental resistance RS is
infinite.
 It is based on the idealization that, once the n-channel
is pinched off, changes in vDS will have no effect on iD.
 The problem is that, in practice, this is not completely
true. Oxford University Publishing
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 5.2.4. Finite Output
Resistance in
Saturation

 Q: What effect will increased vDS have on n-channel once

pinch-off has occurred?
 A: It will cause the pinch-off point to move slightly
away from the drain & create new depletion region.
 A: Voltage across the (now shorter) channel will
remain at (vOV).
 A: However, the additional voltage applied at vDS will
be seen across the “new” depletion region.
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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 5.2.4. Finite Output this is the most important
Resistance in point here
Saturation

 Q: What effect will increased vDS have on n-channel once

pinch-off has occurred?
 A: This voltage accelerates electrons as they reach
the drain end, and sweep them across the “new”
depletion region.
 A: However, at the same time, the length of the n-
channel will decrease.
 Known as channel length modulation.

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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 5.2.4. Finite Output
Resistance in
Saturation

 Q: How do we account for “this

Figure 5.16: Increasing vDS beyond vDSsat causes the
effect” in iD?
channel pinch-off point to move slightly away
 A: Refer to (5.23). from the drain, thus reducing the effective
channel length by L
   valid  vDS vOV  
 when
1 W 2
(eq5.17) iD   nC ox  vOV in A
2 L
1 W 2
(eq5.23) iD   nC ox  vOV 1  vDS  in A
  2    L        
valid when vDS vOV

 A: Addition of finite output Figure 5.18: Large-Signal Equivalent Model of the

resistance (ro). n-channel MOSFET in saturation, incorporating the
output resistance ro. The output resistance
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models the linear dependence of iD on vDS and is
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033) given by (5.23)
 5.2.4. Finite Output
Resistance in
Saturation  i 
(eq5.24) ro   D 
1

 vDS  vGS constant


 Q: How is ro defined?       (5.23)
     
 step #1: Note that ro is the iD  1 W 2 
(eq5.23)     C
n ox  v OV 1   v 
DS 
vDS vDS  2 L 
1/slope of iD-vDS  
characteristic.
      (5.23)
     
 step #2: Define relationship iD  1  W 2 
(eq5.23)    n ox 
 C v OV 1   v DS  
between iD and vDS using vDS vDS  2 L 
(5.23).  
iD 1 W 2
 step #3: Take derivative of (eq5.23)   nC ox  vOV 
this function. vDS 2 L

 step #4: Use above to define
ro. 1 W 2 
1

(eq5.25) ro    nC ox  vOV 

 Note that ro may be defined in 2 L  vGS constant
terms of iD, where iD does not (eq5.24) ro 
1 VA

take in to account Oxford Universitychannel
Publishing
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 iD iD
length modulation…
 5.2.4. Finite Output
Resistance in
Saturation

 Q: What is ?
 A: A device parameter with the
units of V -1, the value of which
depends on manufacturer’s
design and manufacturing
process.
 much larger for newer tech’s
 Figure 5.17 demonstrates the effect
of channel length modulation on Figure 5.17: Effect of vDS on iD in the
vDS-iD curves saturation region. The MOSFET
parameter VA depends on the process
 In short, we can draw a straight
line between VA and saturation. technology and, for a given process,
is proportional to the channel length
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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
L.
 5.3. MOSFET Circuits at
DC

 We move on to discuss how

MOSFET’s behave in dc

DC
circuits.
 We will neglect the effects of
channel length modulation
(assuming  = 0).
 We will work in terms of
overdrive voltage (vOV), which
reduces need to distinguish
between PMOS and NMOS.
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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 Example 5.3: NMOS
Transistor

 Problem Statement: Design

the circuit of Figure 5.21, that
is, determine the values of RD
and RS – so that the transistor
operates at ID = 0.4mA and VD =
+0.5V. The NMOS transistor
has Vt = 0.7V, nCox = 100A/V2,
L = 1m, and W = 32m.
Neglect the channel-length
modulation effect (i. e. assume
that  = 0). Figure 5.21: Circuit for Example
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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033) 5.3.
 Example 5.4:

 Refer to textbook…

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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 Example 5.5: MOSFET

 Problem Statement:
Design the circuit in Figure
5.23 to establish a drain
voltage of 0.1V. What is
the effective resistance
between drain and source
at this operating point?
Let Vtn = 1V and k’n(W/L) =
1mA/V2. Figure 5.23: Circuit for Example
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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)