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Testing Unit V VLSI

This document discusses testing of VLSI circuits. It covers the need for testing at different levels from wafer to system level. There are three main categories of tests - functionality tests, manufacturing tests, and field tests. Manufacturing tests verify that each transistor and gate functions correctly using techniques like IDDQ testing and scan-based approaches. Design for testability methods like scan chains and built-in self-test help make chips more testable. Boundary scan allows testing connections between chips on a board.

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kalavathi devi
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48 views

Testing Unit V VLSI

This document discusses testing of VLSI circuits. It covers the need for testing at different levels from wafer to system level. There are three main categories of tests - functionality tests, manufacturing tests, and field tests. Manufacturing tests verify that each transistor and gate functions correctly using techniques like IDDQ testing and scan-based approaches. Design for testability methods like scan chains and built-in self-test help make chips more testable. Boundary scan allows testing connections between chips on a board.

Uploaded by

kalavathi devi
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© © All Rights Reserved
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Download as PPTX, PDF, TXT or read online on Scribd
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Testing of VLSI Circuits

 Unit V
 18EIE02 VLSI Design
Need for Testing
 Tests fall into three main categories.
 set of tests verifies that the chip performs its intended function –
Functionality test
 tests verify that every transistor, gate, and storage element in the
chip functions correctly. These tests are conducted on each
manufactured chip before shipping to the customer to verify that the
silicon is completely intact. These are called manufacturing tests.
 the complexity of the manufacturing process, not all die on a wafer
function correctly. Dust particles and small imperfections in starting
material or photomasking can result in bridged connections or
missing features. These imperfections result in what is termed a
fault.
Testing a die (chip) can occur at the following
levels
 Wafer level
 Packaged chip level
 Board level
 System level
 Field level
Functional verification – levels of abstraction
A typical test board
 zero insertion force (ZIF) socket for the chip (in the center of the
board), an area for analog circuitry interface (on the left), a set of
headers for logic analyzer connection (at the top and bottom) and a
set of programmable power supplies (on the right). In addition, an
interface is provided for control by a serial port of a PC (at the
bottom left).
Manufacturing Test Principles
 to verify that every gate operates as expected.
 Typical defects include the following:
 Layer-to-layer shorts (e.g., metal-to-metal)
 Discontinuous wires (e.g., metal thins when crossing vertical
topology jumps)
 Missing or damaged vias
 Shorts through the thin gate oxide to the substrate or well
 lead to particular circuit maladies
 Nodes shorted to power or ground
 Nodes shorted to each other
 Inputs floating/outputs disconnected
I/O integrity is also tested
 I/O levels (i.e., checking noise margin for TTL, ECL, or CMOS I/O
pads)
 Speed test
 Case Study – Problem
Automatic testing
Tester load board
Manufacturing Test Principles
 manufacturing test is to screen out most of the defective parts before
they are shipped to customers.
Fault Models
 model for how faults occur and their impact on circuits.
 Stuck at Model
 Short Circuit/ Open Circuit model
 Stuck-At Faults : These faults most frequently occur due to gate
oxide shorts (the nMOS gate to GND or the pMOS gate to VDD) or
metal-to-metal shorts.

 Short-Circuit and Open-Circuit Faults:


Design for Testability
 Ad hoc testing
 Scan-based approaches
 Built-in self-test (BIST)
Adhoc Testing
 Partitioning large sequential circuits
 Adding test points
 Adding multiplexers
 Providing for easy state reset
 bus in a bus-oriented system for test purposes. Each register has
been made loadable from the bus and capable of being driven onto
the bus. Here, the internal logic values that exist on a data bus are
enabled onto the bus for testing purposes.
Scan
Scan
 Convert each flip-flop to a scan register
  Only costs one extra multiplexer
  Normal mode: flip-flops behave as usual
  Scan mode: flip-flops behave as shift register
 In this scheme, every input to the combinational block can be
controlled and every output can be observed.
BIST
 perform operations upon themselves that prove correct operation.
These techniques add area to the chip for the test logic, but reduce
the test time required and thus can lower the overall system cost.
 signature analysis or cyclic redundancy checking - involves using a
pseudo-random sequence generator (PRSG)
PRSG
 Linear Feedback Shift Register
  Shift register with input taken from XOR of state
  Pseudo-Random Sequence Generator
BILBO
 combination of signature analysis and the scan technique creates a
 structure known as BIST—for Built-In Self-Test or BILBO—for Built-
In Logic Block Observation
 In the reset mode (10), all the flip-flops are synchronously
 initialized to 0. In normal mode (11),
 the flip-flops behave normally with their D input and Q output. In
scan mode (00), the flip-flops are configured as a 3-bit shift register
between SI and SO
Built-in Logic Block Observer
IDDQ testing
 method of testing for bridging faults is called IDDQ test (VDD supply
current Quiescent) or supply current monitoring
 CMOS logic gate is not switching - it draws no DC current (except for
leakage).
 bridging fault occurs- a measurable DC IDD will flow
 Testing Process - applying the normal vectors, allowing the signals to
settle, and then measuring IDD.
 IDDQ testing ceases to be effective because variations in
subthreshold leakage exceed currents caused by the faults.
Boundary Scan
 Many system defects occur at the board level, including open or
shorted printed circuit board traces and incomplete solder joints. At
the board level, “bed-of-nails” testers historically were used to test
boards.
 In this type of a tester, the board-under-test is lowered onto a set of
test points (nails) that probe points of interest on the board.
 The increasing complexity of boards and the movement to
technologies such as surface mount technologies (with an absence
of throughboard vias) resulted in system design ers agreeing on a
unified scan-based methodology called boundary scan for testing
chips at the board (and system) level.
 developed by the Joint Test Access Group and hence is commonly
referred to as JTAG.
Boundary testing
I/O pins of each IC on the board are
connected serially in
a standardized scan chain accessed
through the Test Access
Port (TAP) so that every pin can be
observed and controlled
remotely through the scan chain.
References:

 CMOS VLSI Design By Neil Weste , 4th edition.

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