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Chapter 3 - Flip-Flop

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0% found this document useful (0 votes)
84 views39 pages

Chapter 3 - Flip-Flop

Uploaded by

sarmillanrao
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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FLIP-FLOP CHAPTER

3
LEARNING OUTCOME

• Types of Flip-flop
• Operation of each type of flip-flop.
• JK flip-flop to construct T flip-flop
and D flip-flop.
TYPES OF FLIP-FLOP

 SR
 JK
D
T
SR FLIP-FLOP

NOR gate SR Flip-Flop

NAND gate SR Flip-Flop


NOR GATE SR FLIP-FLOP
NOR GATE SR FLIP-FLOP
NAND GATE SR FLIP-FLOP
NAND GATE SR FLIP-FLOP
CLOCKED SR FLIP-FLOP

S Q S Q

CLK CLK

CLK is CLK is
activated by a R Q activated by a R Q
positive going negative going
transition transition

PGT NGT
CLOCKED SR FLIP-FLOP

S
A
C Q

CLK

D Q
B
R
CLOCKED SR FLIP-FLOP

S R Q(t+1) Operation

0 0 Qt hold
0 1 0 reset
1 0 1 set
1 1 1 invalid
EXAMPLE 1

Determine the Q and output waveforms of the flip-


flop in figure (a) below for the S, R, and CLK inputs
in figure (b). Assume that the positive edge-triggered
flip-flop is initially RESET.

SET
S Q
CLK
R CLR
Q
EXAMPLE 1

CLK 1 2 3 4 5 6

(b) R

(c) Q
JK FLIP-FLOP

• Inputs J and K behave like inputs S and R


to set and clear the flip-flop (note that in a
JK flip-flop, the letter J is for set and the
letter K is for clear).
• When logic ‘1’ inputs are applied to both J
and K simultaneously, the flip-flop
switches to its complement state, i.e., if
Q=1, it switches to Q= 0 and vice versa.
JK FLIP-FLOP

J Q
CP
K Q
JK FLIP-FLOP

J A
C Q

clk

K D Q
B
JK FLIP-FLOP

CLK J K OUTPUT

0 0 Hold

0 1 Reset

1 0 Set

1 1 Togol
TIMING DIAGRAM

CLK

Q
EXAMPLE
The waveforms in figure (a) below are applied to the
J, K, and clock inputs are indicated. Determine the Q
output, assuming that the flip-flop is initially
RESET.
SET
J Q

CLK
K CLR
Q
EXAMPLE

CLK 1 2 3 4 5

(a) K

(b) Q No
Toggle Change Reset Set Set
JK FLIP-FLOP WITH
ASYNCHRONOUS INPUT
• For the clocked flip-flops that we have been
studying, the inputs have been referred to as
control inputs.
• These inputs are also called synchronous input,
because their effect on the flip-flop output is
synchronized with the CLK input.
• As we have seen, the synchronous control inputs
must be used in conjunction with a clock signal to
trigger the flip-flop.
JK FLIP-FLOP WITH
ASYNCHRONOUS INPUT

• Most clocked flip-flops also have one or more


asynchronous inputs which operate independently of the
synchronous inputs and clock input.
• These asynchronous inputs can be used to set the flip-
flop to the 1 state or clear the flip-flop to the 0 state at
any time, regardless of the conditions at the other inputs.
• Stated in another way, the asynchronous inputs are
override inputs, which can be used to override all the
other inputs in order to place the flip-flop in one state or
the other.
JK FLIP-FLOP WITH
ASYNCHRONOUS INPUT

J PRE
Q

CLK

K CLR Q
TRUTH TABLE OF JK FLIP-FLOP
WITH AN ASYNCHRONOUS INPUT

INPUT OUTPUT
OPERATION Asynchronous Synchronous Qt+1
preset clear J K Clk
Asynchronous set 0 1 x x x 1
Asynchronous reset 1 0 x x x 0
Invalid 0 0 x x x t+1 (invalid)
hold 1 1 0 0 Qt
reset 1 1 0 1 0
set 1 1 1 0 1
toggle 1 1 1 1 t
EXAMPLE
EXAMPLE 1
EXAMPLE 2
T FLIP-FLOP

• The toggle, or T, flip-flop is a bistable device that


changes state on command from a common input
terminal.
• The T input may be preceded by an inverter. An
inverter indicates a FF will toggle on a HIGH-to-
LOW transition of the input pulse.
• The absence of an inverter indicates the FF will
toggle on a LOW-to-HIGH transition of the pulse.
The most commonly used T FFs are J-K FFs wired
to perform a toggle function
T FLIP-FLOP

T Q T
J Q
CLK
Q K Q
T FLIP-FLOP

T Q

CP

Q
T FLIP-FLOP

Q T Q (t+1)
0 0 0
0 1 1
1 0 1
1 1 0
T FLIP-FLOP
EXAMPLE 1
EXAMPLE 2
D FLIP-FLOP

• The D FF is a two-input FF. The inputs are the data


(D) input and a clock (CLK) input. The clock is a
timing pulse generated by the equipment to control
operations.
• The D FF is used to store data at a predetermined
time and hold it until it is needed. This circuit is
sometimes called a delay FF. In other words, the
data input is delayed up to one clock pulse before it
is seen in the output.
D FLIP-FLOP

D Q D J Q
CP
Q
K Q
D FLIP-FLOP

D
Q

CP
(clo ck puls e)

Q
D FLIP-FLOP

CLK D Q Operation
0 1 0 start
↑ 1 1 store 1
0 0 Q no change
↑ 0 0 store 0
D FLIP-FLOP

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