Department of

Computer Science and Engineering

Course Code Course Title L T P C

10211CS129 Modern Computer Architecture 3 0 0 3

Category : Program Core

Unit-1
 Course Outcomes

CO
Course Outcomes K - Level
No’s

Understand the organization of the Control unit, Arithmetic and

CO1 K2
Logical unit, Memory unit and the I/O unit.

Knowledge Level (Based on revised Bloom’s Taxonomy)

K1-Remember K2-Understand K3-Apply K4-Analyze K5-Evaluate K6-Create

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 TextBooks

1. Hamacher, V.C., Vranesic, Z.G., and Zaky, S.G.,

“Computer Organization”, 5/e. McGraw-Hill. 2014.
[Unit- 1,2]

2. Patterson, D.A., and Hennessy, J.L. , “Computer

Architecture : A Quantitative Approach ”, Morgan
Kaufmann Publishers, , Inc.2017.[Unit -3, 4,5]

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 Unit-1 Basic Structure of a Computer
System
Unit 1 Basic Structure of a Computer System
9 Hours

Functional Units, Basic Operational Concepts, Instructions, Instruction’s cycle, Memory

reference instruction, I/O interruption, Adder and Subtractor circuits, Booth Multiplication

Algorithm, Pipelining Review, control hazards and the motivation for caches, cache

characteristics and superscalar architecture basics.

Why do we need to study computer
architecture?
 Explores how machines are designed, built, and
operate.

 What's inside and how it works will help you

design, develop, and implement applications
better, faster, cheaper, more efficient, and easier

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 Why is Computer Architecture important?

Helps us to understand the functionalities of a system.

Tells us how exactly all the units in the system are arranged and interconnected.
 A programmer can view architecture in terms of instructions, addressing modes and
registers.

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 What is Computer Architecture ?

Set of rules and methods

 Functionality, management and implementation of computers.
The rules by which a system performs and operates.

Computer Architecture can be divided into mainly three categories

Instruction set Architecture or ISA

 Whenever an instruction is given to processor, its role is to read and act accordingly.
 It allocates memory to instructions and also acts upon memory address mode (Direct
Addressing mode or Indirect Addressing mode).

Micro Architecture
Describes how a particular processor will handle and implement instructions from ISA.
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It includes the other entire hardware component within the system such as virtualization,
multiprocessing.

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 Road map of Computer

System design
Software interface Processor Design 10
8 9 Memory
Instruction set architecture

Design of a simple processor

4
ARM assembly Processor system
Pipelining
2 design 11
3
Language Assembly 6 Multiprocessors
7
of bits Building blocks: Computer
language
gates, registers, arithmetic 12
5 and memories I/O and storage
x86 assembly

Software Hardware Hardware

engineer designer designer
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 Functional Units

 A computer in its simplest form is a fast electronic machine.

 It accepts digitize information from the user processes it according to a
sequence of instruction and provides the processor information to the user.
 Components of computer system are hardware and software.

Hardware components are:

1. Input unit
2. Output unit
3. Memory unit
4. CPU

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 Functional Units

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 Functional Units
1. Input unit:

It is used for entering data and programs from user to computer system for
processing.
Most commonly used input device are keyboard and mouse.

2. Output unit:

It is used for displaying the results produced by the system after processing.
Most commonly used output devices are monitor, printer, plotter etc.

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 Functional Units
3. Memory unit:

•It is used for storing data and instruction before and after processing.
•It is divided into primary memory and secondary memory.
•RAM and ROM

Primary memory (volatile main memory):

•It is fast semiconductor RAM.
•It loses instructions and data when power off.
•It used to hold program while they are running.

Secondary memory (non- volatile):

•It is magnetic tapes, magnetic disk are used for the storage of larger
amount of data. and Project
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•A form of memory that retains
(SEPM) data even in the absence of a power source.
•It is permanent storage device.

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 Functional Units

4. Central processing unit (CPU):

•CPU is a brain of the system.
•CPU takes data and instructions from the storage unit and makes all sorts of
calculations based on the instructions gives, type of data provided.

CPU is dived into 2 sections namely:

ALU: arithmetic and logical unit.
•All arithmetic and logical operations are performed by the ALU.
•To perform these operations operands from the main memory are
brought into internal registers of processor.
•After performing operation the result is either stored in the register or memory.
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 Software Components

 Software components

Software is a collection of program Computer software is divided into two broad

categories:

1. System software

2. Application software

1. System software:

• It is collection of programs which is needed in the creation, preparation and

execution of other program.
and
• System software includes editor, assemblers, linker, loader, compilers,

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 Software Components
2. Application software:

Allows to perform specific task on a computer using capabilities of computer.

Application software is to accomplish a task.

Different application software are needed to perform different tasks.

Operating system:

OS Is a collection of routines that tells the computer what to do under a variety of
conditions.

It is used to control the sharing of and interaction among various

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computer units as they execute
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 Basic Operational Concepts

 Instructions take a vital role for the proper working of the computer.
 An appropriate program consisting of a list of instructions is stored in the
memory so that the tasks can be started.
 The memory brings the Individual instructions into the processor, which executes
the specified operations.
 Data which is to be used as operands are moreover also stored in the memory.

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 Basic Operational Concepts

Example:
Add LOCA, R0
This instruction adds the operand at memory location LOCA to the operand which
will be present in the Register R0.
Example can be written as follows:
Load LOCA, R1
Add R1, R0
First instruction sends the contents of the memory location LOCA into processor
Register R0
Meanwhile the second instruction adds the contents of Register R1 and R0 and
places the output in the Register R1.
The memory and the processor are swapped and are started by sending the address
of the memory location to be accessed to the memory unit and issuing the
appropriate control signals.
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The data is then transferred to or from the memory.
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 Instruction Set
 To command a computer hardware, you must speak in language.

 The words of a computer language called instruction. The collection of words is

called instruction set.

 Machine instruction is in the form of binary codes.

 Each instruction of cpu has specific information field which are required to execute

it Such information fields of instruction is called element of instruction.

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 Instruction Set
Instruction types:
Data processing Instruction :
Transfer the data between memory and register.
Arithmetic Instruction :
Performs arithmetic operation using numerical data.
The logical instruction :
Performs logical operation on the bits of a word.

Ex: ADD, SUB, AND, XOR, SHIFT, ADI,INR, DCR, CMP etc…

Data storage: memory instruction

The data has transfer between memory and register. Ex: STR
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 Instruction Set

Data movement: data transfer instruction:

The data has transfer between cpu register and I/O devices. Ex: LOAD,STORE,

MOVE.

Control: Test and branch instruction

Test instruction tests the value of a data word.

Branch instruction depends on decision made. Ex: JMP,JZ(jump on zero),

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JNZ(jump on no zero).
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 Instruction Set
Examples of instruction set:

1.ADD - Add two numbers together.

2.COMPARE - Compare numbers.

3.IN - Input information from a device, e.g., keyboard.

4.JUMP - Jump to designated RAM address.

5.JUMP IF - Conditional statement that jumps to a designated RAM address.

6.LOAD - Load information from RAM to the CPU.

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7.OUT - Output information to device,
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8.STORE - Store information to RAM.

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 Instruction Format

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 Instruction Cont…
Elements of instruction:
1.Operation code(OPCODE): Specifies the operations to be performed.
2.Source/destination operand: Specifies the source/destination for the operand
instruction.
3.Source operand address: Specified the instruction may require one or more
source operands.
4.Destination operand address: The result stored in the destination operand
5.Next instruction address: To fetch the next instruction after completion of
execution of current instruction.

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 Addressing modes

 Addressing modes are the way of specifying an operand or memory address in an

instruction.
 The different ways in which the location of an operand is specified in an instruction are
called address modes.

Types of addressing modes:

1. Register addressing mode

2. Immediate addressing mode.

3. Base or displacement addressing mode

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4. Pc-relative addressing mode
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 Addressing modes Cont…

5.Pseudo- direct addressing mode

6.Register Indirect addressing mode

7.Auto increment addressing mode

8.Auto decrement addressing mode

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 Addressing modes Cont…

1)Register addressing mode:

Is the considered the simplest addressing mode.

Because the operands are in register.
It allows the instructions to be executed much faster. It is a form of direct addressing.

•Ex: R=50 , r=r2

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 Addressing modes Cont…
2) Immediate Addressing Mode:
MIPS immediate addressing means that one operand is a constant
within the instruction itself.
The advantage of using it is that there is no need to have extra memory
access to fetch the operand.
But keep in mind that the operand is limited to 16 bits in size.
000h, 00y,56h, 67a

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 Addressing modes Cont…

3)Base or displacement addressing mode:

Base address is a data or instruction memory location is specified as a signed offset from a register.

It is also known as indirect addressing; a register act as a pointer to an operand located at the memory

location whose address is in the register.

The address of the operand is the sum of the offset value and the base value. The size of the operand is

limited to 16 bits.
r0 A=10
R1 B =20 -----
OPCODE addressing 000lk
field b=50 R2 C=20
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Effective address r4 50 ----
B 000ka
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purtner
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 Addressing modes Cont…

4) PC- relative addressing mode:

It is also known as program counter addressing.

It is a data or instruction where memory location is specified as an offset

relative to the incremented PC.

It is usually used in conditional branches.

Pc stores the address of next instruction to be fetched.

It offset value can be an immediate value or an interpreted label value.

It implements position independent code.

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 Addressing modes Cont…

5) Direct Addressing mode:

It is the memory address which (mostly) embedded in the instructions. It is specifically used for J-type
instructions, j and jal.
The instruction format is 6 bits of opcode and 26 bits for the immediate value.
The effective address will always be a word aligned.

OPCODE addressing
field a=20 memory
A=20
B=10
3=20
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A

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 Addressing modes Cont…

6) Register direct Addressing Mode:

The instruction contains the address of memory which refers the

address of the operand.

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 Addressing modes Cont…
6) Register direct Addressing Mode:

The instruction contains the address of memory which refers the address of the operand.
7) Auto increment addressing mode:

After accessing the operand, the content of this register are incremented to address the next location
Example: Mov R0,(R2)+
•R2=20
8) Auto decrement addressing mode
The content of register specified in the instruction are first decremented and then
used an effective address of the operand
Example : Mov – (R0),R2

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 Representing instructions

 Instructions are kept in computers as a series of high and low electric signals
and represented as number.
 Each piece of an instruction can be considered as an individual number .
 Placing these number side by side forms the instruction.
Instruction format:
A form of representation of an instruction composed of fields of binary numbers.
In MIPS ISA instructions fall into 3 categories:
1. R- format: register format
2. I-format: intermediate format
3. J – format: Jumpand
format
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 Representing instructions Cont..
1. R- format: register format

 Op: basic operation of the instruction, traditionally called the opcode

 Rs: the first register source operand. RS hold one of the argument of the operation
Eg: ADD ro,r1
 Rt: The second register source. Rt hold another arguments of the operation
Eg Mul ro,r1
 Rd: The register destinationand
operand.
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Management
Eg:STR r2
(SEPM)
 Shamt: shift amount. Amount of bit to shift
 Funct: function code. To specify the operation in addition to the opcode.
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Representing instructions Cont..

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 Instruction Cycle

 A program residing in the memory unit of a computer consists of a sequence of instructions.

 These instructions are executed by the processor by going through a cycle for each instruction.

Each instruction cycle consists of the following phases:

1.Fetch instruction from memory.

2.Decode the instruction.

3.Read the effective address from memory.

4.Execute the instruction.

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 Registers
Registers Involved In Each Instruction Cycle:

Memory address registers(MAR) :

It is connected to the address lines of the system bus. It specifies the address in memory for a read or
write operation.

Memory Buffer Register(MBR) :

It is connected to the data lines of the system bus. It contains the value to be stored in memory or the
last value read from the memory.

Program Counter(PC) :

Holds the address of the next instruction to be fetched.

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Holds the last instruction fetched.

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 Major steps in the instruction cycle

Fetch:
The CPU retrieves the instruction from memory.
The instruction is typically stored at the address specified by the program counter
(PC).
The PC is then incremented to point to the next instruction in memory.

Decode:
The CPU interprets the instruction and determines what operation needs to be
performed.
This involves identifying the opcode and any operands that are needed to execute
the instruction

Execute:
The CPU performs the operation specified by the instruction.
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This may involve reading or writing data from or to memory, performing
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arithmetic or logic operations
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program.

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 Major steps in the instruction
 There are also somecycle
additional steps that may be performed during the
instruction cycle, depending on the CPU architecture and instruction set

4.Fetch operands:
 The operands needed for an instruction are fetched during a separate cycle
before the execute cycle.
 This is called the fetch operands cycle.

5.Store results
 some CPUs, the results of an instruction are stored during a separate cycle after
the execute cycle.
 This is called the store results cycle.

6.Interrupt handling:
 In some CPUs, interrupt handling may occur during any cycle of the instruction
cycle. and Project
 An interrupt is a signalManagement
that the CPU receives from an external device or
(SEPM)
software that requires immediate attention.
 When an interrupt occurs, the CPU suspends the current instruction and
executes an interrupt handler to service the interrupt.
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 Memory Reference

The commands or instructions which are in the custom to generate a reference to the memory and
approval to a program to have an approach to the commanded information and that states as to from
where the data is cache continually.

There are seven memory reference instructions

AND

The AND instruction implements the AND logic operation on the bit collection from the register and
the memory word that is determined by the effective address.

The result of this operation is moved back to the register.

ADD
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The ADD instruction adds the content of the memory word that is denoted by the effective address to
(SEPM)
the value of the register.

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 Memory Reference
LDA
The LDA instruction shares the memory word denoted by the effective address to the
register.

STA
This saves the content of the register into the memory word that is defined by the
effective address.
The output is next used to the common bus and the data input is linked to the bus. It
needed only one micro-operation.

BUN
The Branch Unconditionally (BUN) instruction can send the instruction that is
determined by the effective address.
 They understand that the address of the next instruction to be performed is held by the
PC and it should be incremented by one to receive the address of the next instruction in the
sequence. and Project
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If the control needs to implement
(SEPM) multiple instructions that are not next in the sequence,
it can execute the BUN instruction.

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 Memory Reference

BSA
BSA stands for Branch and Save return Address.
These instructions can branch a part of the program (known as subroutine or
procedure).
When this instruction is performed, BSA will store the address of the next
instruction from the PC into a memory location that is determined by the
effective address.

ISZ
The Increment if Zero (ISZ) instruction increments the word determined by
effective address.
 If the incremented cost is zero, thus PC is incremented by 1.
A negative value is saved in the memory word through the programmer.
It can influence the zero value after getting incremented repeatedly.
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Thus, the PC is incremented and the next instruction is skipped.
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 I/O Interrupt

 The method that is used to transfer information between internal storage and

external I/O devices is known as I/O interface.

 A process of data transfer in which an external device or a peripheral informs the

CPU that it is ready for communication and requests the attention of the CPU.

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 Mode of Transfer

The binary information that is received from an external device is usually stored in the
memory unit.
The information that is transferred from the CPU to the external device is originated from
the memory unit.
CPU merely processes the information but the source and target is always the memory unit.
 Data transfer between CPU and the I/O devices may be done in different modes.
Data transfer to and from the peripherals may be done in any of the three possible
ways
1.Programmed I/O.
2.Interrupt- initiated I/O.
3.Direct memory access( DMA).
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 Mode of Transfer
Programmed I/O:
It is due to the result of the I/O instructions that are written in the computer program.
Each data item transfer is initiated by an instruction in the program.
Usually, the transfer is from a CPU register and memory.
In this case it requires constant monitoring by the CPU of the peripheral devices.
Example of Programmed I/O:
The I/O device does not have direct access to the memory unit.
A transfer from I/O device to memory requires the execution of several instructions by
the CPU, including an input instruction to transfer the data from device to the CPU and
store instruction to transfer the data from CPU to memory.
 In programmed I/O, the CPU stays in the program loop until the I/O unit indicates that
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Time-consuming process since it needlessly keeps the CPU busy.
This can be avoided by using an interrupt facility.
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 Mode of Transfer
Interrupt- initiated I/O:

The CPU is kept busy un necessaril yin programmed I/O.

This can be avoided by using an interrupt driven method for data transfer. By using
interrupt facility and special commands to inform the interface to issue an interrupt request
signal whenever data is available from any device.
Mean while the CPU can proceed for any other program execution.
 The interface keeps monitoring the device.
Whenever it is determined that the device is ready for data transfer it initiates an interrupt
request signal to the computer.
 Upon detection of an external interrupt signal the CPU stops momentarily the task that it
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was already performing, branches to the service program to process the I/O transfer, and then
Management
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return to the task it was originally performing.

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 Mode of Transfer
•The I/O transfer rate is limited by the speed with which the processor can test and service a
device.
•The processor is tied up in managing an I/O transfer; a number of instructions must be
executed for each I/O transfer.
Interrupt terms:
Hardware Interrupts: Interrupts present in the hardware pins.
Software Interrupts: These are the instructions used in the program whenever the
required functionality is needed.
Vectored interrupts: These interrupts are associated with the static vector address.
Non-vectored interrupts: These interrupts are associated with the dynamic vector
address.
Maskable Interrupts: These interrupts can be enabled or disabled explicitly.
Non-maskable interrupts: These are always in the enabled state. we cannot disable
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 Mode of Transfer
External interrupts: Generated by external devices such as I/O.
Internal interrupts: These devices are generated by the internal components of the
processor such as power failure, error instruction, temperature sensor, etc.
Synchronous interrupts: These interrupts are controlled by the fixed time interval.
All the interval interrupts are called as synchronous interrupts.
Asynchronous interrupts: These are initiated based on the feedback of previous
instructions. All the external interrupts are called as asynchronous interrupts.

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 Mode of Transfer

Direct Memory Access:

The data transfer between a fast storage media such as magnetic disk and memory

unit is limited by the speed of the CPU.

Thus we can allow the peripherals directly communicate with each other using the

memory buses, removing the intervention of the CPU.

This type of data transfer technique is known as DMA or direct memory access.

During DMA the CPU is idle and it has no control over the memory buses.
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The DMA controller takes over the
(SEPM)
buses to manage the transfer directly between

the I/O devices and the memory unit.

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 Mode of Transfer

 The Bus grant request time.

 Transfer the entire block of data at transfer rate of device because the device is usually
slow than the speed at which the data can be transferred to CPU.
 Release the control of the bus back to CPU So, total time taken to transfer the N bytes =
Bus grant request time + (N) * (memory transfer rate) + Bus release control time.

 Buffer the byte into the buffer

 Inform the CPU that the device has 1 byte to transfer (i.e. bus grant request)

 Transfer the byte (at system bus speed)

 Release the control of the

andbus back to CPU.
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 Adder and Subtractor
Circuits
The basic building blocks that form the basis of all hardware used to perform the arithmetic
operations on binary numbers are half-adder, full adder, half-subtractor, full- subtractor.
Half-Adder:
A half-adder is a combinational circuit that can be used to add two binary bits.
It has two inputs that represent the two bits to be added and two outputs, with one
producing the SUM and the CARRY

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Block schematic
(SEPM) of half-adder

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 Half Adder

The truth table of a half-adder, showing all possible input combinations and the
corresponding outputs are shown below.

Inputs Outputs

A B Carry (C) Sum (S)

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

Truth table of half-adder

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 Half Adder

The Boolean expressions for the SUM and CARRY

Sum, S= A’B+ AB’= AB
Carry, C = A . B
The first one representing the SUM output is that of an EX-OR gate, the second one representing the
CARRY output is that of an AND gate.

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Logic Implementation of Half-adder

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 Full Adder
Full-Adder:
A full adder is a combinational circuit that forms the arithmetic sum of three input bits. It
consists of 3 inputs and 2 outputs.
Two of the input variables, represent the significant bits to be added. The third input
represents the carry from previous lower significant position.

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Block schematic of full-adder

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 Full Adder

The full adder circuit overcomes the limitation of the half-adder, which can be used to add two bits
only. There are three input variables, eight different input combinations are possible.

Inputs Outputs
A B Cin Sum (S) Carry (Cout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
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1
Management1 1 1 1
(SEPM)
Truth Table:

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The Boolean expressions for the SUM and CARRY outputs are given by the equations,
Sum, S = A’B’Cin+ A’BC’in + AB’C’in + ABCin
Carry, Cout = AB+ ACin + BCin .
The logic diagram for the above functions is shown as,

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Implementation of full adder with two half-adders and an OR gate
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 Half -Subtractor

A half-subtractor is a combinational circuit that can be used to subtract one binary digit
from another to produce a DIFFERENCE output and a BORROW output.
The BORROW output here specifies whether a ‗1‘ has been borrowed to perform the
subtraction.
Truth Table

Input Output
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Man A B Difference (D) Borrow (Bout)

0 0 0 0

Block schematic of half-subtractor

0 1 1 1
agement
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1 0 1 0

1 1 0 0

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 Half -Subtractor

The Boolean expressions for the DIFFERENCE and BORROW

Difference, D = A’B+ AB’= A  B
Borrow, Bout= A’ . B
The logic diagram of the half adder is,

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Logic Implementation of Half-Subtractor

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 Full-Subtractor

The truth table for full-subtractor

Inputs Outputs

A B Bin Difference(D) Borrow(Bout)

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1
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 Full-Subtractor

The Boolean expressions for the DIFFERENCE and BORROW

Difference, D = A’B’Bin+ A’BB’in + AB’B’in + ABBin
Borrow, Bout = A’B+ A’Cin + BBin .

The logic diagram for the above functions

The logic diagram

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 BOOTH MULTIPLICATION ALGORITHM

•The booth algorithm is a multiplication algorithm that allows us to multiply the two
signed binary integers in 2's complement, respectively.
•It is also used to speed up the performance of the multiplication process. It is very
efficient too.
•It works on the string bits 0's in the multiplier that requires no additional bit only
shift the right-most string bits and a string of 1's in a multiplier bit weight 2 k to
weight 2m that can be considered as 2k+ 1 - 2m.
BOOTH MULTIPLICATION ALGORITHM

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 BOOTH MULTIPLICATION ALGORITHM

 In the above flowchart, initially, AC and Qn + 1 bits are set to 0, and the SC is a sequence
counter that represents the total bits set n, which is equal to the number of bits in the
multiplier.

 There are BR that represent the multiplicand bits, and QR represents the multiplier bits.

 After that, we encountered two bits of the multiplier as Q n and Qn + 1, where Qn represents
the last bit of QR, and Qn + 1 represents the incremented bit of Qn by 1.

 Suppose two bits of the multiplier is equal to 10; it means that we have to subtract the
multiplier from the partial product in the accumulator AC and then perform the arithmetic
shift operation (ashr).

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 BOOTH MULTIPLICATION ALGORITHM

 If the two of the multipliers equal to 01, it means we need to perform the addition of the
multiplicand to the partial product in accumulator AC and then perform the arithmetic
shift operation (ashr), including Qn + 1.

 The arithmetic shift operation is used in Booth's algorithm to shift AC and QR bits to the
right by one and remains the sign bit in AC unchanged.

 And the sequence counter is continuously decremented till the computational loop is
repeated, equal to the number of bits (n).

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 BOOTH MULTIPLICATION ALGORITHM

 Booth algorithm gives a procedure for multiplying binary integers in signed 2’s
complement representation in efficient way, i.e., less number of additions/subtractions
required.

 It operates on the fact that strings of 0’s in the multiplier require no addition.

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 BOOTH MULTIPLICATION ALGORITHM

 Normal Multiplication

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 BOOTH MULTIPLICATION ALGORITHM

Normal Multiplication

 Booth algorithm requires examination of the multiplier bits and shifting of thepartial
product.

 Prior to the shifting, the multiplicand may be added to the partial product,subtracted
from the partial product, or left unchanged

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 BOOTH MULTIPLICATION ALGORITHM

Booth Multiplier Recoding Table

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 BOOTH MULTIPLICATION ALGORITHM

Booth multiplication

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 BOOTH MULTIPLICATION ALGORITHM

Booth multiplication

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 PIPELINING

 Pipelining is an implementation technique in which multiple instructions are overlapped

in execution.

SEQUENTIAL EXECUTION METHOD

pipelining is nearly universal.
Example:
1. Place one dirty load of clothes in the washer.
2. When the washer is finished, place the wet load in the dryer.
3. When the dryer is finished, place the dry load on a table and fold.
4. When folding is finished, ask your roommate to put the clothes away.

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 PIPELINING

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 PIPELINING

PIPELINE EXECUTION METHOD

The same principles apply to processors where we pipeline instruction-execution. MIPS

instructions classically take five steps:

1.Fetch an instruction from memory

2. Decode the instruction
3. Execute the instruction
4. Read memory to get input
5. Write the result back to memory

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 PIPELINING

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 PIPELINING

 INSTRUCTIONS FETCH

 The IF stage is responsible for obtaining the requested instruction from memory.

 The instruction and the program counter are stored in the register as temporary
storage.

DECODE INSTRUCTION

 The DI stage is responsible for decoding the instruction and sending out the
various control lines to the other parts of the processor.

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 PIPELINING

CALCULATE OPERANDS

• The CO stage is where any calculations are performed.

• The main component in this stage is the ALU.
• The ALU is made up of arithmetic, logic and capabilities.

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 PIPELINING

FETCH OPERANDS AND EXECUTE INSTRUCTION

• The FO and EI stages are responsible for storing and loading values to and from
memory.

• They also responsible for input and output from the processor respectively

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PIPELINING

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 Control Hazards

 Control hazard occurs whenever the pipeline makes incorrect branch

prediction decisions, resulting in instructions entering the pipeline that must be

discarded.

 A control hazard is often referred to as a branch hazard.

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 Control Hazards-Occurance

 The flow of program/instruction execution is controlled by branch instructions.

 In higher-level languages, conditional statements are used for repetitive loops or

condition testing (correlate with while, for, if, case statements).

 These are converted into one of the BRANCH instruction variations.

 To understand the programme flow-the value of the condition being tested.

 As a result, when the decision to execute one instruction is reliant on the result of

another instruction, such as a conditional branch, which examines the condition’s

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 CACHE MEMORY

Cache memory is a small-sized type of volatile computer memory that provides high-
speed data access to a processor and stores frequently used computer programs,
applications and data.

Cache memory faster than main memory.

Cache memory, also called CPU memory, It can access more quickly than it can
regular RAM.
This memory is typically integrated directly with the CPU chip or placed on a
separate chip that has a separate bus interconnect with the CPU.
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 CACHE MEMORY

 Consider the simple arrangement in

following figure

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 CACHE MEMORY

When a read request is received from the processor, the contents of the memory
location are transferred into the cache one word at a time.

When the program references any of the locations in this block, the desired
contents are read directly from the cache.

Usually the cache memory can store a reasonable number of blocks at any given
time, but this number is small compared to the total number of block in the main
memory.

The correspondence between the main memory blocks and cache is specified by
a mapping function.

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 CACHE MEMORY

MAPPING FUNCTIONS:

There are three types of mapping techniques used in cache memory system

Direct mapping
Associative mapping
Set associative mapping

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 CACHE MEMORY

Direct mapping:

The simplest way to determine cache locations in which to store memory blocks
is the direct mapping technique.
Consider a cache of 128 blocks.
The jth block in main memory is mapped onto block j modulo 128 of the cache.
Thus, whenever one of the main memory blocks 0, 128, 256… is loaded in the
cache, it is stored in cache block 0. Block1, 129, 257… are stored in cache block
1, and so on.
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CACHE MEMORY

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 CACHE MEMORY

Associative mapping

The main memory block can be placed into any cache block position.  In this
case, 12 tag bits are required to identify a memory block when it is resident in the
cache.
The tag bits of an address received from the processor are compared to the tag
bits of each block of the cache to see if the desired block is present.
This is called the associative mapping technique. COMPUTER
ARCHITECTURE 15
It gives complete freedom
and in choosing the cache location in which to place the
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Thus, the space in the cache can be used more efficiently.

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 CACHE MEMORY

Mapping method.

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 CACHE MEMORY

Set Associative mapping

A combination of the direct and associative mapping techniques can be used.

Blocks of the cache are grouped into sets, and the mapping allows a block of the main
memory to reside in any block of a specific set.
 Hence the contention problem of the direct method is eased by having a few choices
for block placement.
At the same time, the hardware cost is reduced by decreasing the size of the associative
search.
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This is called the set associative
Managementmapping technique is shown in figure.
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CACHE MEMORY

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 CACHE MEMORY

It has the cache with two blocks per set.

In this case, memory blocks 0, 64, 128,….4032 map into cache set 0, and
they can occupy either of the two block positions within this set.
Having 64 sets means that the 6 bit set field of the address determines
which set of the cache might contain the desired block.
The tag field of the address must then be associatively compared to the tags
of the two blocks of the set to check if the desired block is present.
This two way associative
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 CACHE MEMORY

Measuring and Improving Catch Performance

Two different techniques are used to improve cache performance,

Reducing the miss rate.

 Reducing the miss penalty by adding additional catch (multilevel caching)
The performance of the cache memory system incorporated with CPU execution
time.
Then the formula is, CPU execution time = (CPU clock cycles + Memory stall
clock cycles) * Clock cycle time
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The effectiveness of cacheManagement
memory is based on locality of reference.
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 CACHE MEMORY

Types of Locality
Temporal locality
Spatial locality

Temporal locality:
Temporal locality means recently executed instructions are executed very
soon.
Spatial locality :
Spatial locality means that instructions in close proximity to a recently
executed instruction (with respect to the instructions addresses) are also likely
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 SUPERSCALAR ARCHITECTURE

 Superscalar architecture is a method of parallel computing used in many

processors.

 In a superscalar computer, the central processing unit (CPU) manages

multiple instruction pipelines to execute several instructions concurrently
during a clock cycle.

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 SUPERSCALAR ARCHITECTURE

 Superscalar architecture is a method of parallel computing used in many

processors.

 In a superscalar computer, the central processing unit (CPU) manages

multiple instruction pipelines to execute several instructions concurrently
during a clock cycle.

 Superscalar architectures include all pipelining features although there are

several instructions executing simultaneously within the same pipeline.

 Superscalar design methods normally comprise parallel register renaming,

parallel instruction decoding, speculative execution & out-of-order
execution.
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SUPERSCALAR ARCHITECTURE

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 SUPERSCALAR ARCHITECTURE

Advantages of superscalar architecture

 A superscalar CPU can execute more than one instruction per clock cycle.

 Because processing speeds are measured in clock cycles per second

(megahertz), a superscalar processor will be faster than a scalar processor
rated at the same megahertz.

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 SUPERSCALAR ARCHITECTURE

Application of superscalar architecture

 Desktop and laptop computers often use superscalar execution.

 A superscalar processor scans the program during execution to find sets of

instructions that can be executed together.

 Digital signal processing systems are more likely to use very-long instruction
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Department of Computer Science and Engineering