Microprocessors’

Internal Architectures

Course Teacher:
Deboky Saha (DES)
Contractual Lecturer
Department of Computer Science & Engineering
BRAC University.

Course ID: CSE - 341

Course Title: Microprocessors
Lecture References:
 Book:
 Microprocessors and Interfacing: Programming and Hardware,
Chapter # 2, Author: Douglas V. Hall

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Internal Structure of a Microprocessor

Address bus
ALU Register
Section
Data bus

Control and timing section

Control bus

Block Diagram of a Microprocessor

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Examples of Microprocessor
 Intel 8085
 The 8085 microprocessor was introduced by Intel in the year
1976.
 8-bit microprocessor with 16-bit address bus and 8-bit data bus.
 This microprocessor is an update of 8080 microprocessor.
 It is an 8-bit microprocessor with a 40 pin Dual in Line
Package (DIP)

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Examples of Microprocessor
 Intel 8086
 The microprocessor 8086 can be considered to be the basic
processor for the Intel X86 family from 1978.
 It has a 20-bit address bus along with 16-bit data bus.
 With the knowledge of 8086 16-bit processor, one can study the
further versions of this processor 80286, 80406 and Pentium.
 Intel 8088
 The Intel 8088 have 20-bit address bus with 8-bit data bus
(allowing the use of cheaper and fewer supporting logic chips).
 8086/8088 have the same instruction set, it forms the basic set
of instructions for other Intel families.

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8-Bit 8085 Intel Processor Architecture
(skip)
8-bit_Internal_databus

Accumulator Temp. Reg Flag Reg Instruction B C

Reg

D E

Arithmetic H L
and Logic
Unit
Instruction Stack Pointer
decoder
Program Counter
Incrementer/ Decrementer
Address latch

Address Buffer A8-A15 Data/address Buffer

AD0-AD7
Timing and Control unit
8 - bit External
Data bus
Clock Write Read RAM memory
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8-Bit 8085 Intel Processor (Pin Diagram)
(skip)

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8085 Registers and Memory
(skip)
 Registers:
 Information is stored in registers
 Registers are classified according to the functions they
perform
 64 Kbytes of memory

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8085 Register Categories
(skip)
 Accumulator – 8 bit register which holds the latest result from ALU
 B, C, D, E, H and L are general purpose registers
 HL pair can be used for indirect addressing as well
 Program counter – 16 bit register which holds the address of the
next instruction to be executed
 Instruction Register – It holds the instruction that is currently being
processed.
 Stack Pointer is used during subroutine calling and execution.
 Address Latch – It increments/ decrements the address before sent
to the address buffer

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8085 Register Categories
(skip)
 Various Flags
 Sign Flag: If the result of the latest arithmetic operation is having MSB (most-
significant byte) ‘1’ (meaning it is a negative number), then the sign flag is set to
‘1’. Otherwise, it is reset to ‘0’ which means it is a positive number.

 Zero flag: If the result of the latest operation is zero, then zero flag will be set to
‘1’; otherwise it be reset to ‘0’.

 Auxiliary Carry Flag: This flag is not accessible to programmer. This flag will
be used by the system during BCD (binary-coded decimal) operations.

 Parity Flag: If the result of the latest operation is having even number of ‘1’s,
then this flag will be set to ‘1’ Otherwise this will be reset to ‘0’. This is used for
error checking.

 Carry Flag: If the result of the latest operations exceeds 8-bits then this flag will
be set to ‘1’. Otherwise it be reset to ‘0’.
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8086

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16-Bit 8086 Intel Processor Architecture

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16-Bit 8086 Intel Processor (Pin Diagram)MAXIMUM
MODE
MINIMUM
MODE

GND 1 40 Vcc
AD14 AD15
AD13 A16,S3
AD12 A17,S4
AD11 A18,S5
AD10 A19,S6
AD9 /BHE,S7
AD8 MN,/MX
AD7 /RD
AD6 /RQ,/GT0 HOLD
AD5
8086 /RQ,/GT1 HLDA
AD4 /LOCK /WR
AD3 /S2 IO/M
AD2 /S1 DT/R
AD1 /S0 /DEN
AD0 QS0 ALE
NMI QS1 /INTA
INTR /TEST
CLK READY
GND 20 21 RESET

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Organization of the 8088/8086
 2 main components:
1. Execution Unit (EU)
2. Bus Interface Unit (BIU)

 EU: ALU + Registers (AX, BX, CX, DX, SI, DI, BP, and SP)
+ FLAGS register.
 ALU: performs arithmetic & logic operations.
 Registers: store data
 FLAGS Register: Individual bits reflect the result of a computation.

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Organization of the 8088/8086
 BIU: facilitates communication between the EU & the
memory or I/O circuits.
 Responsible for transmitting addresses, data, and control
signals on the buses.
 Registers (CS, DS, ES, SS, and IP) hold addresses of
memory locations.
 IP (instruction pointer) contain the address of the next
instruction to be executed by the EU.

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The queue (in BIU)

While the EU is decoding an instruction or executing

an instruction which does not require the use of buses,
the BIU fetches up to next six instruction bytes for the
following instructions. The BIU stores the prefetched
bytes in FIFO register called queue. When EU is ready
for its next instruction from the queue, it simply reads
from the queue in the BIU. This is much faster.
Fetching the next instruction while the current
instruction executes is called pipelining.

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Procedure
 The segment registers (CS,DS,SS,ES) and offset
register(IP) present in BIU containing the addresses of
segments and offset (present in memory) calculates the
physical address in ∑.
 After calculation of physical address the instructions are
carried out from the Memory Interface and stored in queue
 The instruction is then send to the Control system (present
in EU) where it gets decoded
 After that the instruction gets executed with the help of
data registers (AX,BX,CX,DX) and ALU

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8086 Registers and Memory
Number of Registers: 14, each of that16-bit registers
Memory Size: 1M Bytes (Address Bus – 20 bit)

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8086 Register Categories
 Data registers (4):
General data registers
hold data for an
operation (AX, BX,
CX, DX).
 Address registers (9):
(Segment, Pointer and
Index registers) hold
the address of an
instruction or data.
 Status register (1):
FLAG register keeps
the current states of the
processor.
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General Data Registers
 These are 16-bit registers and can also be used as two 8 bit
registers: low and high bytes can be accessed separately
 AX (Accumulator)
 Most efficient register for arithmetic, logic operations and data transfer:
the use of AX generates the shortest machine code.
 In multiplication and division operations, one of the numbers involved
must be in AL or AX
 BX (Base)
 The base address register (offset)
 CX (Counter)
 Counter for looping operations: loop counter, in REP instruction, and in
the shift and rotate bits
 DX (Data)
 Used in multiply and divide, also used in I/O operations

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Memory Segment and Segment Registers
 Four Segment Registers in the BIU are used to hold the
upper 16-bits of the starting addresses of four memory
segments, namely
 Code segment CS: holds segment number of the code segment.
 Data Segment DS: holds segment number of the data segment.
 Extra Segment ES: extra segment : holds alternate segment
number of the data segment.
 Stack Segment SS: holds segment number of the stack segment
and used when sub-program executes.
 Codes , data , and stack are loaded into different memory
segments (registers).

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Memory Segment and Segment Registers

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Pointer and Index Registers
 Used for offset of data, often used as pointers. Unlike segment
registers, they can be used in arithmetic and other operations.
 SP (Stack Pointer):
 Used with SS for accessing the stack segment.
 Holds Offset address relative to SS
 Always points to word (byte at even address)
 An empty stack will had SP = FFFEh
 BP (Base Pointer):
 Used with SS to access data on the stack. However, unlike
SP, BP can be used to access data in other segments.
 Primarily used to access parameters passed via the stack
 Holds Offset address relative to SS
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Pointer and Index Registers
 SI (Source Index):
 Source of string operations. Used with DS (or ES).
 Can be used for pointer addressing of data with effective address (EA)
 Used as source in some string processing instructions
 Offset address relative to DS
 DI (Destination Index):
 Destination of string operation. Used with ES (or DS).
 Can be used for pointer addressing of data
 Used as destination in some string processing instructions
 Offset address relative to ES
 IP (Instruction pointer):
 Points to the next instruction.
 Offset address relative to CS

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Flag Register
 Flags Register: A 16-Bits register specify status of CPU and
information about the results of the arithmetic operations.
 Flags Register determines the current state of the processor.
 It is modified automatically by CPU after mathematical
operations, this allows to determine the type of the result, and
to determine conditions to transfer control to other parts of the
program.
 Generally you cannot access these registers directly.

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Flag Register
 It is generally divided into two and they are Status flag and Control Flag
Status Flags:
 Carry Flag (CF)- Carry out from MSB. If there is no carry then CF=0, if
there is carry in the MSB, then C.F=1
In other words, this flag is set to ’1’ when there is an unsigned overflow.
For example when you add bytes 255 + 1 (result is not in range 0...255).
When there is no overflow this flag is reset to 0.
 Parity Flag (PF) - this flag is set to ’1’ when there is even number of one
bits in result, and reset to ’0’ when there is odd number of one bits.
 Auxiliary Flag (AF) - set to ’1’ when there is a carry from lower nibble
to higher nibble.
 Zero Flag (ZF) - set to ’1’ when result is zero. For non-zero result this
flag is reset to ’0’.

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Flag Register
 Sign Flag (SF) - This flag takes the value of the most
significant bit. Thus, when set to ’1’ the result is negative.
When result is positive it is reset to ‘0’.
 Overflow Flag (OF) - set to ’1’ when there is a signed
overflow. For example, when the result go out of the
range
(-128 to -1) and
(0 to 127)

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Control Flags:

The control flag is used to control certain operations. They

are changed by the programmer.

 Trap Flag (TF) - Used for on-chip single-step debugging.

 Interrupt enable Flag (IF) - when this flag is set
to ’1’ CPU reacts to interrupts from external devices.
 Direction Flag (DF) - this flag is used by some
instructions to process data chains, when this flag is set
to ’0’ - the processing is done forward, when this flag is
set to ‘1’ the processing is done backward.

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Flags in a nutshell

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Flag Register (Example)

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Thank You !!

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