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8088 Microprocessor 03

The document discusses using a line decoder to interface a microprocessor's memory addressing lines with multiple memory chips. It explains that a 10-bit microprocessor with 1KB of memory could be interfaced with 8 128x8 memory chips using a 3-bit line decoder to select the appropriate chip. The line decoder decodes the 3 most significant address lines to activate one of its 8 outputs, each connected to the chip enable of a memory chip. This allows the microprocessor to address its full 1KB memory space across the 8 chips. Diagrams and truth tables are provided to illustrate the decoding process.

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23 views

8088 Microprocessor 03

The document discusses using a line decoder to interface a microprocessor's memory addressing lines with multiple memory chips. It explains that a 10-bit microprocessor with 1KB of memory could be interfaced with 8 128x8 memory chips using a 3-bit line decoder to select the appropriate chip. The line decoder decodes the 3 most significant address lines to activate one of its 8 outputs, each connected to the chip enable of a memory chip. This allows the microprocessor to address its full 1KB memory space across the 8 chips. Diagrams and truth tables are provided to illustrate the decoding process.

Uploaded by

fa20-bce-047
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Microprocessor Systems and

Interfacing
CPE 342
Dr. Abbas Javed
([email protected])
Microprocessor 8088

 Outline
 Memory Interfacing with 8088 using Line
Decoders

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Why Line Decoder?
 Let’s assume a very simple microprocessor with
10 address lines (1KB memory)
 Let’s assume we wish to implement all its
memory space and we use 128x8 memory chips
where starting address is F0000H
 SOLUTION
 We will need 8 memory chips (8x128=1024)
 We will need 3 address lines to select each one of the
8 chips
 Each chip will need 7 address lines to address its
internal memory cells

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A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Starting F0000 H 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Ending F007F H 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1

F0080 H 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

F00FF H 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

F0100 H 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

F017F H 1 1 1 1 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1

F0180 H 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0

F01FF H 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1

F0200 H 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0

F027F H 1 1 1 1 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1

F0280 H 1 1 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0

F02FF H 1 1 1 1 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1

F0300 H 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0

F037F H 1 1 1 1 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1

F0380 H 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0

F038F H 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1

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Memory Interfacing using Line
Decoder

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Line Decoder

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Line Decoder

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Construct 64KB Memory by interfacing eight 8KB EEPROM. Starting address of memory is
F0000H

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
F0000 H 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

F1FFF H 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1

F2000 H 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

F3FFF H 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1

F4000 H 1 1 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0

F5FFF H 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1

F6000 H 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0

F7FFF H 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

F8000 H 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

F9FFF H 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1

FA000 H 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

FBFFF H 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1

FC000 H 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FDFFF H 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1

FE000 H 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0

FFFFF H 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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Memory Interfacing using Line
Decoder

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Line Decoder

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Line Decoder
 The outputs of the decoder in the figure, are
connected to eight different 2764
 EPROM memory devices.
 The decoder selects eight 8K-byte blocks of memory for a
total capacity of 64K bytes.
 The decoder’s outputs are connected to the CE inputs of
the EPROMs,
 The RD signal from the 8088 is connected to the OE inputs
of the EPROMs
 In this circuit, a three-input NAND gate is connected to
address bits A19–A17

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Line Decoder
 When all three address inputs are high, the output of this
NAND gate goes low and enables input G2B of the
74LS138.
 Input G1 is connected directly to A16.
 In order to enable this decoder, the first four address
connections (A19–A16) must all be high.
 Address inputs C, B, and A connect to microprocessor
address pins A15–A13.
 These three address inputs determine which output pin
goes low and which EPROM is selected whenever 8088
outputs a memory address within this range to the memory
system.

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Line Decoder

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Memory Bank
Memory Type Part number Storage capacity
27C16 2KB
27C64 8KB
EPROMs 27C128 16KB
27C256 32KB
27C512 64KB
61C16 2KB
SRAMs
62C256 32KB
28C16 2KB
EEPROMs 28C32 4KB
28C256 32KB

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