RISC-V Introduction

Welcome to the Open era of computing!

Who is RISC-V
RISC-V International is a global nonprofit
association based in Switzerland. Founded in 2015
as the RISC-V Foundation with 29 members, RISC-
V is now a truly global organization with
2k+ members in more than 70 countries.
RISC-V supports the free and open RISC instruction set architecture and extensions
delivering a new level of free, extensible software and hardware freedom on
architecture, paving the way for the next 50 years of computing design and innovation.

RISC-V is part of the Linux Foundation, bringing the community together to build and maintain the open RISC-V ISA.
 RISC-V is the free and open
Instruction Set Architecture…

Welcome to the …Driven through open

collaboration
Open era of …Enabling freedom of design

computing.
across all domains and
industries

…Cementing the strategic

foundation of semiconductors
Disruptive Technology
Barriers Legacy ISA RISC-V ISA

Complexity 1500+ base instructions 47 base instructions

Incremental ISA Modular ISA

Design freedom $$$ – Limited Free – Unlimited

License and Royalty fees $$$ Free

Design ecosystem Moderate Growing rapidly. Numerous

extensions, open & proprietary
cores

Software ecosystem Extensive Growing rapidly

 Industry innovation on RISC-V
Hardware
– RV64, multi-heart
CPUs, vectors,
Hardware bit manipulation,
– RV32, privilege hypervisors, debug mode –
modes, interrupts –
AI SoCs
Hardware
– RV32 – IoT SoCs Application
Microcontrollers processors
Proof of Concept SoCs
Hardware Minion processors for Software Software
Complexity

ISA Definition power management, RTOS Linux

Test Chips communications, … Firmware Drivers
AI Compilers
Software Software
Tests Bare metal software
2010 – 2016 2017 – 2018 2019 – 2020 2021
 RISC-V tech roadmap
RISC-V Innovation Roadmap AI SoCs, Application
IoT SoCs processors, Linux Industry Adoption
Microcontrollers Drivers, AI Compilers Proliferation of RISC-V CPUs across
RTOS, Firmware Dev Board program performance and application spectrum
Development tools Development Partners RISC-V dominant in universities
Proof of Concept SoCs
Technical Steering RISC-V Labs, Security Strategic and growing adoption in HPC,
Test Chips Minion processors for Committee, response process, AI automotive, transportation, cloud,
power management, HPC SIG, SIG, Graphics SIG, industrial, communications, IoT,
Software tests
communications GlobalPlatform Android SIG, enterprise, consumer, and other
Linux port
Bare metal software partnership Communications SIG applications

2010 – 2016 2017 2018 2019 2020 2021

2022 2023 2024 2025
ISA Definition RV32 RV32I and RV64I Arch compatibility
Zfinx RV32E and RV64E
Base instructions: framework, ZiHintPause 64 bit and 128 bit addresses*
RISC-V
Integer, floating Processor trace BitManip
Foundation Vector Atomic and quad-widening*
point, multiply and Vector
divide, atomic, and Quad floating point in integer registers*
RISC-V Profiles &
compact instructions Platforms Crypto Vector*
Crypto Scalar Trusted Execution phase 2*
Priv modes,
Virtual Memory Jit pointer masking & I/D synch*
Interrupts,
Hypervisor & Advanced BitManip phase 2*
exceptions, memory
interrupt architecture Cache management phase 2*
model, protection,
and virtual memory Cache mgt ops
… and more
Code size reduction*
Trusted Execution
Environment* Technical Deliverables
* On track, subject to change
P (Packed SIMD)*
RISC-V Ecosystem
HPC Data Center
Consumer IoT Networking
Applications

Runtimes

SAIL
Research

Operating Systems

Reliable, Serviceable, Diagnostic

SPIK

Hypervisor
E
Profilers + Analysis Tools

Services
Boot
Training

Performance
Academia

Security

Debug
Formal
Simulators

Architecture Tests
Compilers
CI/Testing

SAIL Model
ISA

RTL DV

Implementation Design & Microarchitecture

Silicon Soft IP
 Unconstrained Opportunity
RISC-V Business Model
Barriers removed Collaboration
partners
▪ Design risk
▪ Cost of entry Development Supply chain
▪ Partner limitations
▪ Supply chain

Expanded Expanded
markets geographies

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 Beyond removing barriers,
RISC-V fuels our community to
seize growing opportunities
 By 2025, 40% of
application-specific
integrated circuits (ASICs)
will be designed by
OEMs, up from around
30% today.

Custom ICs Based on RISC-V Will Enable

Cost-Effective IoT Product
Differentiation

Gartner, June 2020

Source: Gartner
RISC-V’s open model will spur adoption by cloud service
providers and streamline resources for chip vendors

Source: Gartner
ID: 46523_C
30 billion
connected
and IoT
devices
demand
security and
custom
processors

Source: Strategy Analytics

Rapid RISC-V growth led by industrial

62.4 billion RISC-V CPU cores

by 2025
Semico Research predicts the
market will consume 62.4
billion RISC-V CPU cores by
2025, a 146.2% CAGR 2018-
2025. The industrial sector to
lead with 16.7 billion cores.

Source: Semico Research Corp

Nearly a quarter of designs incorporate RISC-V

Wilson Research Group/Siemens

found that 23% of ASIC and
FPGA projects incorporated
RISC-V in at least one processor
in a double-blind 2020 study.
RISC-V IP, SW, and Tools build momentum

The total market for

RISC-V IP and
Software is expected
to grow to $1.07
billion by 2025 at a
CAGR of 54.1%

Source: Tractica
Data Center Telecom &
Cloud, HPC
Top providers like Amazon and Communications
Alibaba are designing their own Rapid evolution in 5G, handsets,
chips. and base stations grows with each

RISC-V
New features specific to HPC generation of hardware and
such as Vector and larger Virtual increased capability
address space

Automotive Consumer and adoption

IoT devices
spans
Transforming from
autonomous vehicles to
infotainment to safety, the Incredible innovation is driving
whole vehicle relies on volume with billions of connected
innovative electronics. devices in the next 5-10 years.
industries
AI / ML Edge Computing
Artificial intelligence is A distributed, open architecture
incorporated across many decentralizes processing power,
areas including Industrial IoT, reduces latency, and supports IoT
manufacturing, and financial performance in low bandwidth
environments.
 More than 2,200 RISC-V Members
across 70 Countries

102 Chip 4 Systems

ODM, OEM
SoC, IP, FPGA

4 I/O 13 Industry
Memory, network, storage Cloud, mobile, HPC, ML, automotive

17 Services
95 Research
Fab, design services Universities, Labs, other alliances

42 Software
1,900+ Individuals
Dev tools, firmware, OS
RISC-V engineers and advocates

RISC-V membership grew 133% in 2020.

June 2021
In 2021, RISC-V membership has already doubled. 17
 Dedicated Community
Services Fab,
design services Chip SoC, IP, FPGA

I/O Memory, Universities

network, storage and Research

Software Dev tools, Industry cloud,

firmware, OS mobile, HPC, ML,
automotive

Press and Analysts Investors and Funding

sources
Individual Advocates
18
Incredible industry progress
• The European Processor Initiative finalized the • Alibaba unveiled RV64GCV core in its Xuantie
first version of its RISC-V accelerator 910 processor for cloud and edge servers.
architecture and will deliver test chip in 2021.
• Microchip released the first SoC FPGA
• The RIOS Lab announced PicoRio, an development kit based on the RISC-V ISA.
affordable RISC-V open source small-board
computer available in 2021. • Andes released superscalar multicore and L2
cache controller processors.
• Imperas announced first RISC-V verification
reference model with UVM encapsulation. • StarFive released the world’s first RISC-V AI
visual processing platform
• Seagate announced hard disk drive
controller with high-performance RISC-V CPU. • SiFive unveiled world’s fastest development
board for RISC-V Personal Computers.
• GreenWaves ultra-low power GAP9
hearables platform enabling scene-aware • Micro Magic announced an incredibly fast 64-
and neural network-based noise reduction. bit RISC-V core achieving 5GHz and 13,000
CoreMarks at 1.1V.
 … 4k+ individuals in 60+ RISC-V work
groups and committees
… 330+ RISC-V solutions online
including cores, SoCs, software, tools, and
developer boards
RISC-V is the … 29 local RISC-V community groups,

foundation of with more than 5,400 engineers

… We’re in the news! We have 40k+

the Open era of followers on social media and

across the last year, we have participated in

computing 135+ news articles along with

amplifying RISC-V community news 450+
times.
Technical Compatibility & Visibility
Verification Amplify member news,
Deliverables Testing and compatibility
content, and success with
Technical governance press and analysts
resources
Build technical deliverables Original content programs
Work groups Compatibility tests
RISC-V, industry, and regional
events

Learning & Talent Advocacy + Alliances Marketplace

Multi-level online learning RISC-V Ambassadors Exchange
Connecting universities with Geo and industry alliances Online marketplace of
labs, tests, and curricula Local developer groups and providers, products, services,
RISC-V Training Partners events and learn
Technical developer forums

RISC-V delivers incredible

member support
 RISC-V Technical Programs
RISC-V Platform
A common, reusable
runtime environment that
operating systems and
applications can target to
improve portability and
reuse. Provides
interoperability assurance.
RISC-V Developer RISC-V Development RISC-V Lab
Boards Partner Institutions that host RISC-V Compatible
RISC-V Profiles
Available to spur Recognizes the a lab with RISC-V Architectural Tests
Refers to a base ISA and
innovation, provide investment and hardware for created to help ensure
one or more extensions
hands-on education, dedication of CI/testing and that software written will
that are specified as a
and engage early organizations making general availability run on implementations
group so that applications
adopters to test and significant technical sandboxing. that comply with that
can be compiled once, run
develop. contributions to RISC- profile. Branding
on different
V. available for
implementations, and get
compatibility.
the same results.
Profiles and Platforms
ISA Profiles System Platforms
● A set of extensions that are compatible ● A set of features that are
● Extension types: required, optional, compatible
unsupported, or incompatible ● Includes ISA Profiles, software
● Two profile types: and hardware system
○ Application (RVAyy): Linux-class and components, standardized
other embedded designs with more hardware/software interfaces,
sophisticated ISA needs etc
○ Microcontroller (RVMyy): Cost- ● Two Platform types: OS/A and
sensitive application-optimized M (naming TBD)
embedded designs running bare- ● Ability to move an executable
metal or simple RTOS environments from one implementation to
● Running the same sequence of instruction another and get the same results
between implementations are RISC-V are RISC-V Compatible
compatible

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 RISC-V tech roadmap

Engaging RISC-V community in technical work

that matters
• Profiles. standard set of instructions and state • We are revamping documentation, fully adopting
• An implementer should be able to run the same AsciiDoc, enhancing the specifications with
instructions on multiple implementations and get the same glossaries and indexes, and common formal
results. diagram insertion.
• Platforms. standard set of features for an • We have a number of engagement programs
execution environment (ie Linux or Zephyr) underway
• If you adhere to a Platform then you should be able to run • RISC-V Development Partners - institutions (CAS, RIOS,
the same executable on 2 different platforms and get the IITM) help develop ecosystem software for extensions
same results (excluding timing differences, etc.)
• RISC-V Labs - institutions build labs with RISC-V based
• Platforms include things Profiles, Device tree, ABIs, etc. board and servers to both run regression testing and to
• Extensions for 2021. vector processing, provide the community with an area to sandbox
cryptography, bit manipulation, packed decimal, • RISC-V Developer board program - seed 1000 boards to
trusted execution environment, and virtual academia and early adopters by June 2022

memory. • Joint working group on Coherence between Chips

Alliance and RISC-V as well as a standing security group
together with GlobalPlatform.
 RISC-V is a community of passionate,
dedicated, and invested stakeholders

As individuals
Build RISC-V into
As companies your company
As universities
As public institutions and non-profits strategy, and your
As nations
personal mission
As one Global, connected movement
25
“The future of American industry “Though the architecture was created a
depends on open source tech, … decade ago by university professors,
RISC-V is gaining traction in the RISC-V has been building its ecosystem
hardware manufacturing space for years and has started to hit its stride
throughout the world, because it with big licensees like Western Digital,
lowers barriers to entry and increases SiFive, and even NVIDIA itself.”
chip development speed.” -- VentureBeat
-- Wired

“If it succeeds, RISC-V could lower the cost of developing a new chip and help
companies of all sizes to build exactly the processors they need.”
-- Engadget
 Marketing and Visibility benefits
Share your products and progress with RISC-V!
RISC-V Events
Participating with RISC-V in industry events
● Shows your support for open source and RISC-V
● Opportunity to demonstrate your knowledge and leadership to the
community
● Demo your products and collect leads
RISC-V Blog

The RISC-V blog program is a great way to showcase leadership and industry
commentary, as well as share technical information on your work with RISC-V.

Members can submit content to publish on riscv.org and we promote on social,

as well as a link to the member website to drive traffic.
Case Studies
Case studies help elevate the technical conversations to business
objectives and challenges, showing the use and adoption of RISC-V
across multiple industries and use cases.

As a member, we will publish your case study!

Case studies will be highlighted on our website and shared via our wide-reaching media channels
and analyst relationships.
Content - Social
RISC-V is happy to share community, member, and Ambassador
content via our social channels!

● Members can submit original content for our posting on our social channels
● Members and the community can submit content for re-sharing.
Press and Analysts

● Share member and community news “In the News”

● Highlight member announcements via social
● Provide RISC-V team member quotes for member press releases
● Options to submit member news and announcements and participate in
media panels.
Branding
As a member, use RISC-V branding in your marketing materials!
Branding Guidelines and logos
 Working Groups
Join, participate, and engage with the RISC-V Community!
Marketing Committee + Working Groups
Participate in the marketing committee to engage with your peers,
learn about member marketing benefits, and contribute.
Marketing Committee
Primary communication tool with members on RISC-V marketing initiatives.
Meetings: 2nd Tuesday of the month, 8am PT (5pm CEST)

Marketing Content Committee

Discuss content topics such as website, exchange, and research.
Meetings: Last Tuesday of the month: 8am PT (5pm CEST)

Marketing Events Committee

Discuss upcoming events and actions as well as event plans for future
Meetings: Every other Thursday: 9am PT (6pm CEST)
Technical Working Groups
The technical groups are the heart of RISC-V. These groups create and maintain the hardware ISA
and other items around it, including test and debug frameworks, software specs, and other technical
artifacts. Visit our Working Groups page to find groups that fit your interests.
 Group/Meeting Types & Responsibilities
Group Responsibilities

Technical Steering Committee (TSC) Delegation of responsibilities to organizational components below it, strategy, escalations, group & chair & preliminary charter
approvals, ratification. voting (most discussion and notification by email, web page listing and supporting docs, automated
voting system). The TSC has voting members and non-voting attendees. The voting members include premiers and HC and IC
chairs. (non-voting attendees are advisors and RISC-V staff -- no organization can be represented more than once)

Chief Technology Office (CTO) Runs TSC voting process, both Chairs meetings, Strategy, organization, IT, roadmap, resources, escalations,

ISA Committees (IC) Approve and oversee package for TSC vote for the creation of ISA Extension TGs and filling the chair and vice-chair vacancies
for its TGs. Develop strategy for the groups under it and complete coverage of areas of responsibility under it including gaps.

Horizontal Committees (HC) Approve and oversee non-extension TGs, and has responsibilities to make sure that all Extension TGs cover the area overseen
by the HC before ratification, Responsible for developing a holistic strategy and reaching out to the external ecosystem and
community groups.

Horizontal Subcommittees (HSC) It is a nested HC.

Task Groups (TG) Must have charter that defines a small set of deliverable work products: extension specifications, standards, requirements, best
practices, etc.. TGs under the unpriv and priv SC can have ISA extension work products. TGs under HCs should not have ISA
extension work products.

Special Interest Groups (SIG) Develop strategy for complete coverage of areas of responsibility under it including gaps. Provides continuity on the topic of
TGs is may request be created. SIGS produce no work product. Can be created by the TSC, ICs or HCs with TSC approval not
Meeting required. Responsibilities

Committee Chairs Meeting TSC strategy discussions. Invitees are IC chairs & HC chairs, RISC-V staff, TSC, and advisors and ad-hoc invitees.

Chairs Meeting Invitees are RISC-V staff, Chairs & Vice Chairs of all ICs, HCs, HSCs, TGs, & SIGs. Policy approval, general governance, escalations,
exceptions, final charter approval, voting as appropriate.
Special Interest Groups (SIGs)
The SIGs have conversations and drive requirements in key industry
and technology areas.

SIG Academia and Training SIG High Performance Computing (HPC)

Coordinate outreach to the open source community as
Meetings: Monthly on 3rd Thurs: 4pm PT
well as researchers and educators in academia, and to
curate and recommend training materials to both
academics and professional training organizations. SIG Functional Safety
Meetings: Every other Thursday: 8am PT (5pm CEST) Meetings: Every other Thursday: 8am PT (5pm CEST)

SIG Soft CPU

 The Community
Promote your products and people!
RISC-V Alliances
RISC-V regional and industry alliances provide events, maintain relationships, and
create multiple feedback channels in a way that no single organization could do on
its own. See our alliances page for the full listing.
Regional Alliances Industry Alliances
industry alliances create multiple feedback channels on both
Communicate locally, provide local events, and maintain technical and non-technical topics that help both the RISC-V
relationships in a way that no single organization could do on community and the industries using the RISC-V technology.
its own.

40
RISC-V Training Partners
RISC-V Training Partners are focusing on RISC-V training in a professional setting.
The Training Partner Program extends the breadth and reach of RISC-V knowledge,
providing opportunities for a broader audience to learn. See our
Training Partner page for more information on our training partners or how to
become a RISC-V Training Partner.
RISC-V Exchange
The RISC-V Exchange provides a window into work that people have
accomplished around the world in the RISC-V community, including
physical hardware, IP cores, and a great deal of software.
● Available Boards
● Available Cores & SoCs
● Available Software

To add your products to the Exchange, fill out this Google Form.
Email [email protected] with any questions.
RISC-V Ambassador Program
RISC-V Ambassadors are individuals passionate about RISC-V and
dedicated to growing and engaging the RISC-V community.
Ambassadors are RISC-V experts and work together with RISC-V to ensure our global momentum
and adoption. Successful ambassadors include engineers, developers, bloggers, influencers,
evangelists who are already engaged with RISC-V in some way, including contributing to work
groups, online groups, community events, training, workshops, and more.

The RISC-V Ambassador Program empowers community members with tools and resources to:
● Promote RISC-V projects and technology
● Educate a local community on the RISC-V mission and technical aspects
● Engage RISC-V member participation and community growth

Learn more
Joining RISC-V International
 Meet the RISC-V Team

Calista Redmond Kim McMahon Stephano Cetola Mark Himelstein

CEO Director of Visibility and Director Technical CTO
Community Engagement Programs

Brett Preston
Jenni McGinnis Jeff Scheel Megan Lehn Thea Aldrich
Program Manager
Program Manager Technical Program Program Manager Marketing
Manager Manager
 2k+ RISC-V Members
across 70 Countries

94 Chip 4 Systems
SoC, IP, FPGA ODM, OEM

4 I/O 13 Industry
Memory, network, storage Cloud, mobile, HPC, ML, automotive

12 Services 81 Research
Fab, design services Universities, Labs, other alliances

40 Software 1,000+ Individuals

Dev tools, firmware, OS RISC-V engineers and advocates

December 2020
In 2020, RISC-V membership grew 133% 46
 ✔ Accelerate technical traction and insight

✔ Contribute technical priorities, approaches, and code

Benefit ✔ Gain strategic and technical advantage

of ✔ Increase visibility, leadership, and market insight

✔ Fill and increase engineering skills, retain and attract

joining ✔
talent

Build innovation partner network and customer

RISC-V ✔
pipeline

Deepen, engage, and lead in local and industry

developer network

✔ Showcase RISC-V products, services, training, and

resources
 Membership Options
Premier Member Benefits Strategic Member Benefits Community Member Benefits
• Board seat and Technical Steering • 3 Board reps elected for the Strategic tier, • Two Board representatives
Committee seat included for $250k level including Premier members that do not • 1 Community Board representative, elected
• Technical Steering Committee seat included otherwise have a board seat • 1 Individual Board representative, elected
for $100k level • Eligible to lead workgroup and/or committee
• Eligible to lead workgroup and/or committee • Member logo / name listing on RISC-V
• Use of RISC-V Trademark for website, by member level
• Use of RISC-V Trademark for commercialization • 1 case study a year
commercialization • Member logo / name listing on RISC-V • 1 blog per quarter
• Member logo / name listing on RISC-V website, alphabetical with Strategic • 1 social media spotlight per quarter
website, alphabetical with Premier members members • Event sponsorship discount
• Solution / Product listing highlighted on • Solution / Product listing highlighted on the
RISC-V Exchange, noted with member level RISC-V Exchange, noted with member level
• 4 case studies a year • 1 case study a year
• 2 blogs per month • 1 blog per month
• 2 social media spotlights per month • 1 social media spotlight per month
• Spotlight member profile • Event sponsorship discount
• Event sponsorship discount

Premier Requirements Strategic Member Requirements Community Requirements

• Membership open to any type of legal entity • Membership open to any type of legal entity • Membership open to
• $250k Annual membership fee that includes • Annual membership fee based on employee ○ academic institutions,
Board seat and TSC seat size ○ non-profits,
• $100k Annual membership fee that includes • 5,000+ employees: $35k ○ individuals not representing a legal
TSC seat • 500-5,000 employees: $15k entity
• <500 employees: $5k • No annual membership fee
• <10 employees & company <2 yrs old:
$2k
Technical Architecture Visibility
Compatibility Amplify member news,
Deliverables Testing and compatibility suites
content, and success with
Guard against fragmentation press and analysts
Architecture tests
Build technical deliverables Original content programs
Collaborate with technical RISC-V, industry, and regional
working groups & SIGs, events

Learn Advocacy + Alliances Marketplace

Multi-level online learning RISC-V Ambassadors Exchange
Connecting universities with Geo and industry alliances Online marketplace of
labs, tests, and curricula Local developer groups and providers, products, services,
RISC-V Training Partners events and learn
Technical developer forums

RISC-V delivers incredible

member support
 Thank you
Questions: [email protected]