Scribd
Upload
103 views

The 8086 Microprocessor: Ayesha Naureen

The 8086 microprocessor is a 16-bit processor with a 16-bit data bus and 20-bit address bus. It can address up to 1 MB of memory using segmentation. It has general purpose registers, flag registers, and instruction pointer register to facilitate execution. It prefetches instructions into an internal queue for pipelining. Segment registers and stack pointer register are used for memory addressing.

Uploaded by

Naveed Ramzan
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
103 views

The 8086 Microprocessor: Ayesha Naureen

The 8086 microprocessor is a 16-bit processor with a 16-bit data bus and 20-bit address bus. It can address up to 1 MB of memory using segmentation. It has general purpose registers, flag registers, and instruction pointer register to facilitate execution. It prefetches instructions into an internal queue for pipelining. Segment registers and stack pointer register are used for memory addressing.

Uploaded by

Naveed Ramzan
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 16

The 8086 Microprocessor

Ayesha Naureen

The 8086 Microprocessor

16-bit Microprocessor

ALU, internal registers and most of the instructions work with 16-bit binary word. Read or write data to a memory/port either 16bits or 8 bit at a time. Address up to 220 = 1,048,576 memory locations Each of the 1,048,576 memory addresses of the 8086 represents a bytewide location.

16-bit Data Bus

20-bit Address Bus


Words will be stored in two consecutive memory locations. If the first byte of a word is at an even address, the 8086 can read the entire word in one operation. If the first byte of the word is at an odd address, the 8086 will read the first byte of the word in one operation, and the second byte in another operation.

The 8086 Microprocessor Family Overview

Processor
8085 8088

Data Bus
8 8

Address Bus
16 20

Max. Addressable Memory


65,536 1,048,576

8086
80286 80386 80486 80586/Pentium(Pro)

16
16 32 32 64

20
24 32 32 32

1,048,576
16,777,21 4,294,976,296 4,294,976,296 4,294,976,296

8086 Internal Architecture

Bus Interface Unit Sends out addresses Reads data Writes data

INSTRUCTION STREAM BYTE QUEUE

Execution Unit Where to fetch instructions or data from? Decodes instructions Executes instructions

Execution Unit: Control Circuitry, Instruction Decoder, ALU

Control Circuitry

Directs internal operations Translates instructions fetched from memory into a series of actions. Add, Subtract, AND, OR, XOR, Increment, Decrement, Complement, Shift

Instruction Decoder

ALU

Execution Unit: Flag Register

A flag is a flip-flop which indicates some condition produced by the execution of an instruction or controls certain operations of the EU. A 16-bit flag register in the EU contains nine active flags.

Execution Unit: Flag Register


Type Status Flag Name Function CF PF AF ZF Indicates if the instruction generated a carry out of the MSB. Indicates if the instruction generated a result having an even number of 1s. Indicates if the instruction needed an adjustment after BCD arithmetic Indicates if the instruction generated a zero result.

SF
OF

Indicates if the instruction generated a negative result.


Indicates if the instruction generated a signed result that is out of range.

Control Flag

TF
IF DF

Puts the processor into a single-step mode for program debugging.


Enables or disables external interrupts. Controls the direction of the string manipulation instructions.

Execution Unit: General Purpose Registers


EU has eight general purpose registers: AH, AL, BH, BL, CH, CL, DH and DL. The H represents the high-order or most-significant byte and the L represents the low- order or least-significant byte. Used to hold intermediate results. Each of these registers may be used separately as 8-bit storage areas or combined to form one 16-bit storage area. AX: AH-AL BX: BH-BL CX: CH-CL DX: DH-DL The AL register is also called as the Accumulator. For 16-bit operations, AX is called the accumulator.

Bus Interface Unit: The Queue

While EU is decoding/executing an instruction, BIU fetches up to six instruction bytes for the following instructions. The BIU stores these prefetched instructions in a first-in-first-out register called a queue. When EU is ready for next instruction, it reads the instruction byte from the queue. Speeds up the execution process.

Exception: JMP, CALL instructions.

Fetching the next instruction while the current instruction executes is called pipelining.

Bus Interface Unit: Segment Registers


20-bit addresses Address any of 220 or 1,048,576 bytes in memory. But at any given time, 8086 works with only four 65,536 byte data segments. Four segment registers hold the upper 16-bit of the starting addresses of the four memory segments. These are: Code Segment (CS): Instructions are fetched from this segment Data Segment (DS): Program variables and data are held in this area Stack Segment (SS): Stack is a memory area set aside to store addresses and data while a subprogram executes. Extra Segment (ES): Also used for data storage Each segment is made up of an uninterrupted section of memory locations.

Bus Interface Unit: Segment Registers


FFFFFH 7FFFFH 64K 70000H 5FFFFH 64K 50000H 4489FH 64K 348A0H Code Segment Base CS = 348AH Stack Segment Base SS = 5000H Top of Code Segment Extra Segment Base ES = 7000H Top of Stack Segment Highest Address Top of Extra Segment

2FFFFH
64K 20000H 00000H Physical Address

Top of Data Segment

Memory

Data Segment Base DS = 2000H Lowest Address

Bus Interface Unit: Instruction Pointer Register

CS contains the upper 16 bits of the starting address of the segment from where instructions are being fetched. How to get the address of the next instruction to be fetched? Instruction Pointer (IP) Register IP holds the 16-bit address or offset of the next code byte within the code segment. This value is added to the segment base address in CS to produce the required 20-bit physical address. Each time the execution unit accepts an instruction, the instruction pointer, is incremented to point to the next instruction in the program.

Bus Interface Unit: Instruction Pointer Register


CS 348A0 IP + 4214 Physical --------Address 38AB4
4489FH Top of Code Segment

38AB4H

Code Byte

IP=4214H

Segementbase:offsetform 348A:4214
348A0H Code Segment Base CS = 348AH Memory

Physical Address

Stack Segment Register and Stack Pointer Register

Stack Segment (SS) contains the upper 16 bits of the starting address of the stack segment. Stack Pointer (SP) register in EU holds the 16-bit offset from the start of the stack segment to the memory location where a word was most recently stored. Top of Stack: Memory location where a word was most recently stored. The physical address for a stack read or stack write is produced by adding the contents of SP with the segment base address.

Stack Segment Register and Stack Pointer Register


SS 50000 SP + FFE0 Physical --------Address 5FFE0
5FFFFH Top of Stack Segment

5FFE0H

Top of Stack

SP=FFE0H

SS:SP5000:FFE0
50000H Stack Segment Base SS = 5000H Memory

Physical Address

Execution Unit: Pointer & Index Registers


Base Pointer (BP) Register Source Index (SI) Register Destination Index (DI) Register Can be used for temporary data storage. But main function: Hold the 16-bit offset of a data word in one of the segments. For example:

SI can be used to hold the offset of a data word in the data segment. Physical address of word: Data Segment Base (DS) + SI

You might also like