Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

References:
 Enoch O. Hwang, “Digital Logic And Microprocessor Design
with VHDL”, Brooke/Cole , 2005.
 M. M. Mano and C. R. Kime, “Logic and Computer Design
Fundamentals”, Pearson – Prentice Hall, 2004.
 James K. Peckol , “Embedded Systems: A Contemporary Design
Tool”, Oxford Consulting Ltd, 2006.
 Tammy Noergaard, “Embedded Systems Architecture: A
Comprehensive Guide for Engineers and Programmers”, Elsevier
Inc, 2005.
 J. L. Hennessy and D. A. Patterson , “Computer Architecture: A
Quantitative Approach”, Elsevier Inc, 2007.
 J. L. Hennessy and D. A. Patterson , “Computer Organization
and Design: The Hardware/Software Interface”, Elsevier Inc, 5th
edition, 2014.

Dr. Ibrahim Qamar 1

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

What Is an Embedded System (ES)?
 ES refers to a system that is enclosed or embedded in a
larger system.
 ES is a combination of hardware parts, software parts,
and some other components that are brought together
into an application (like a cell phone, a music player, a
network router, or an aircraft guidance system).
 ES techniques allow us to make products that are
smaller, faster, more reliable, and cheaper.
 ES is an applied computer system
 Limited in hardware and/or software functionality than a
personal computer (PC).
 Designed to perform a dedicated function.

Dr. Ibrahim Qamar 2

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Embedded System Examples
Market Embedded Device
Automotive - Ignition System
- Engine Control
- Brake System (i.e., Antilock Braking System)
Consumer Electronics - Digital and Analog Televisions
- Set-Top Boxes (DVDs, VCRs, etc.)
- Personal Data Assistants (PDAs)
- Kitchen Appliances (Refrigerators, Toasters,
Microwave Ovens)
- Automobiles
- Toys/Games
- Telephones/Cell Phones/Pagers
- Cameras
- Global Positioning Systems (GPS)

Dr. Ibrahim Qamar 3

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Embedded System Examples
Market Embedded Device
Industrial Control - Robotics and Control Systems
(Manufacturing)
Medical - Infusion Pumps
- Dialysis Machines
- Prosthetic Devices
- Cardiac Monitors
Networking - Routers
- Hubs
- Gateways
Office Automation - Fax Machine
- Photocopier
- Printers
- Monitors
- Scanners
Dr. Ibrahim Qamar 4
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Embedded System Examples
Anti-lock brakes Modems
Auto-focus cameras MPEG decoders
Automatic teller machines Network cards
Avionic systems Network switches/routers
Battery chargers On-board navigation
Camcorders Photocopiers
Cell phones Portable video games
Cell-phone base stations Printers
Cordless phones Scanners
Cruise control Smart ovens
Curbside check-in systems Speech recognizers
Digital cameras Stereo systems
Dishwashers Teleconferencing systems
Disk drives Televisions
Electronic card readers Temperature controllers
Electronic instruments Theft tracking systems
Electronic toys/games TV set-top boxes
Factory control VCR’s, DVD players
Fax machines Video game consoles
Fingerprint identifiers Video phones
Home security systems Washers and dryers
Life-support systems
Medical testing systems

Dr. Ibrahim Qamar 5

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

The Embedded Systems Model

Dr. Ibrahim Qamar 6

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

The Embedded Systems Model
- ES have at least one layer (hardware) or all layers
(hardware, system and application software) into which
all components fall.
- The hardware layer contains all the major physical
components of the ES.
- The system and application software layers (if any)
contain all of the software located on and being
processed by the embedded system.

Dr. Ibrahim Qamar 7

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Embedded System main Components
DataPath and
Control
(Computing
(Core

Input Output

Memory

Dr. Ibrahim Qamar 8

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Embedded System main Components
- ES in general consists of the following Components :
 DataPath and Control Circuit (Computing Core).
 This unit Represents the central hardware component in any
ES.
 It interacts with and utilizes the remaining components of the
system to implement the required application.
 The Datapath consists of registers and function unit like ALU
 Memory,
 Holds collections of Programs (Software and Firmware).
 Store Input and Output Data as well as the intermediate
computations results .

Dr. Ibrahim Qamar 9

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Embedded System main Components
- ES in general consists of the following Components :
 Input and Output Blocks
 The Input Block provides the port receiving Data or Signals
from the outside world.
 The Output Block provides the port sending Data or Signals to
the outside world.
 Both Blocks are connected to the Core and/or Memory.

-Microprocessors can be used to design ES because they

consists of datapath and control circuit.
-Microcontrollers can also be used to implement ES.
-ES can also be implemented using ASICs or FPGA.
Dr. Ibrahim Qamar 10
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Classification of Embedded Systems
1. Small Scale Embedded Systems:
- Designed with a single 8- or 16-bit Microcontroller.
- They have little hardware and software complexities.
- May be battery operated .
- The main programming tools used are: An editor,
assembler and cross assembler, specific to the
microcontroller or processor used.
- ‘C’ language is used for developing these systems.
- The software has to fit within the memory available on
the microcontroller.
- When system is running continuously, limit of power
dissipation is required .
Dr. Ibrahim Qamar 11
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Classification of Embedded Systems
2. Medium Scale Embedded Systems:
- Designed with a single or few 16- or 32-bit
microcontrollers or DSPs or Reduced Instruction Set
Computers (RISCs).
- They have both hardware and software complexities.
- The main programming tools used are: RTOS, Source code
engineering tool, Simulator, Debugger and Integrated
Development Environment (IDE).
- These systems may also employ Application Specific
System Processor (ASSP) and Intellectual Property (IP)
for bus interfacing, encrypting, deciphering, data
transformation, TCP/IP protocol stacking and network
connecting functions if needed.
Dr. Ibrahim Qamar 12
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Classification of Embedded Systems
3. Sophisticated Embedded Systems:
- They have enormous hardware and software complexities
and may need scalable processors or configurable
processors and programmable logic arrays.
- They are used for applications that need hardware and
software co-design and integration in the final system.
- Certain software functions such as encryption and
deciphering algorithms, data transformation, TCP/IP
protocol stacking and network driver functions are
implemented in the hardware to obtain additional speeds.

Dr. Ibrahim Qamar 13

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Building an Embedded System
 For microprocessors based ES, The microprocessor and
other hardware elements are connected via the system
bus.
 The system bus is actually subdivided into Address,
Data, and Control.
 A typical ES comprises hardware and software
components.

Dr. Ibrahim Qamar 14

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Building an Embedded System
 The microprocessor controls the whole system by
executing a set of instructions called firmware that is
stored in ROM in the memory subsystem.
 When power is first turned on, the microprocessor
addresses a predefined location then fetches, decodes
and executes one instruction after another.
 Many of the embedded systems, especially those used in
control systems, embedded hardware is used in a loop as
shown in the next figure.
 The software program used to control this loop is an
infinite loop as shown in the following code fragment.

Dr. Ibrahim Qamar 15

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Building an Embedded System

while(1)
{
Embedded Program
}
Dr. Ibrahim Qamar 16
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Building an Embedded System
 Time is often an essential constraint in an embedded
application.
 An ES is called Real Time if it must respond to
designated external or internal events within a specified
time interval.
 If a system failure occurs in an ES when a time
constraint is not met, the system is called Hard Real
Time System, otherwise it is a Soft Real Time system.

Dr. Ibrahim Qamar 17

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

The Embedded Design and Development Process
Hardware Software
Architecture Architecture
User Specification Specification
Inputs

Requirement Hardware Software System

Analysis Design Design Integration
Requirements Block Module Verified
Definition Diagram Specifications System
Hardware Software System
Specification
Implementation Implementation Validation
Functional Module Validated
Specification Prototype Object Code System
System Hardware Software Operation and
Architecture Testing Testing Maintenance

Verified Verified
Hardware Software
Dr. Ibrahim Qamar 18
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

The Embedded Design and Development Process
 The previous diagram gives the development process
and identifies the major elements of the development
life cycle of a contemporary ES.
 The hardware portion of the life cycle involves the
design, development, and test of the physical system
architecture, packaging, the printed circuit boards, and
ultimately the individual components.
 The software portion programs the tasks or algorithmic
portion of the application.
 The software may be written in a high level language,
assembler, or a mixture of the two.

Dr. Ibrahim Qamar 19

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

The Embedded Design and Development Process
 An integral part of embedded systems development, is
to make trade off speed, size, power, cost, weight, or
time constraints to meet specified constraints or to
improve performance.

Dr. Ibrahim Qamar 20

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Hardware Components Required for ES
The following components are required for the design of ES:
- Input:
 Sensors for sensing and measuring physical quantity.
Examples for these sensors are:
 CCD or CMOS (Image sensors)
 Bio-metrical sensors (for authentication ) like Finger
print , Iris scan and Face recognition.
 Temperature sensors
 Pressure sensors
 Proximity sensors (for measuring distance)
 Hall Effect Sensors (for Measuring Magnetic Fields)
 Many other types of sensors.
Dr. Ibrahim Qamar 21
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Hardware Components Required for ES
The following components are required for the design of ES:
- Input:
 Sample-and-hold circuits.
 A/D-converters.

-Communication Media:
May be wireless media (radio frequency, infrared), optical
media (fibers) and/or wires.
Examples for this media are:
 Wireless communication Like:
 Bluetooth.
 wireless version of Ethernet.
Dr. Ibrahim Qamar 22
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Hardware Components Required for ES
The following components are required for the design of ES:
- Communication Media:
 Wire communication Like:
 CAN (Controller Area Network).
 SPI (Serial peripheral interface)
 Ethernet.

Dr. Ibrahim Qamar 23

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Hardware Components Required for ES
The following components are required for the design of ES:
- Processing Units:
 Processing Units for ES may be one or more of the
following:
 ASICs (application-specific integrated circuits) using
hardwired multiplexed designs. They are used for high-
performance applications and for large markets
 Reconfigurable logic (Like FPGA).
 Processors or microcontroller. They are the most
suitable components for ES regarding Cost, Power, and
code efficiency.

Dr. Ibrahim Qamar 24

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Hardware Components Required for ES
The following components are required for the design of ES:
- Memories:
 Memories of all kinds are required for ES:
 ROM (Mainly Flash Memory)
 RAM (either DRAM or SRAM)

Dr. Ibrahim Qamar 25

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Hardware Components Required for ES
The following components are required for the design of ES:
- Outputs:
 ES may require output devices like the following:
 Displays (like LEDs, Seven Segments and LCD
displays).
 Electro-mechanical devices (Like Motors) .
 Analog (require D/A-converters) as well as digital
output devices.
 Actuators.

Dr. Ibrahim Qamar 26

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Arithmetic and Logic Unit ALU
- The ALU Performs the arithmetic and logic
operations required by the processor.
- The required operation is selected using X X
control signals given to the ALU (e.g. K1 to ALU Z
K5).
- The Inputs of the ALU are taken from Y Y
registers X and Y (or from a memory
K5 K4 K3 K2 K1
location) and the output of the operation is
stored in a register Z (or a memory
location).
- Some of the operations has one i/p operand
only and the others have two i/p operands.
Dr. Ibrahim Qamar 27
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Arithmetic and Logic Unit ALU
- An important part of the ALUs found in all microprocessors
is the Flag or Status Register which consists of independent
bits.
- The number of bits in this register varies from processor to
another.
- In x86 processors this register consists of 6 bits or flags
named, Z (Zero), C (Carry), P, (Parity) O (Overflow), H (half
Carry) and S (Sign).
- This Register stores a summary of the ALU result. (e.g. if the
result of the operation is zero Z=1, if the operation gives
carry C=1 and so on).

Dr. Ibrahim Qamar 28

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Arithmetic and Logic Unit ALU
- The ALU operations may be as shown in this table:
K5 K4 K3 K2 K1 Operation Category
0 0 1 0 0 Z=X+Y
0 0 1 0 1 Z = X + Y + CF Arithmetic
0 0 1 1 0 Z=X–Y
0 0 1 1 1 Z = X – Y – CF
0 0 0 0 1 Z=X+1
0 0 0 1 1 Z=X–1
0 1 X 0 0 Z = X AND Y
0 1 X 0 1 Z = X OR Y Logic
0 1 X 1 0 Z = X XOR Y
0 1 X 1 1 Z = NOT X
1 0 0 0 0 Z = SHL (X)
1 0 0 0 1 Z = SHR (X) Shift
1 0 0 1 0 Z = SAL (X)
1 0 0 1 1 Z = SAR (X)
1 0 1 0 0 Z = ROL (X)
1 0 1 0 1 Z = ROR (X)
1 0 1 1 0 Z = RCL (X)
1 0 1 1 1 Z = RCR (X)
Dr. Ibrahim Qamar 29
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Register Transfer Logic RTL
- It is an essential part in the Computing Core.
- It consists of Registers connecting together with a
function Unit (like ALU, FPU,…etc.).
- These Registers are used for temporary storage of data
and/or instructions of the computing core.
- Some of these registers are special registers (used for
dedicated functions) and others are General Purposes
Registers.
- These Registers are connected together through Transfer
Path called Bus (or Busses).
- Busses are simply collections of wires that are carrying
related electrical signals from one place to another.
Dr. Ibrahim Qamar 30
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Register Transfer Logic RTL
- The Buses connecting the registers and the function units
are one or more of the following categories:
 Multiple-Busses Multiplexer–Based,
Single-Bus Multiplexer–Based, or
Single-Bus Tri-State.

Dr. Ibrahim Qamar 31

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Register Transfer Logic RTL
1. Multiple-Busses Multiplexer–Based RT
- Sometimes connecting registers
together is essential with each
register has its own bus.
- This can be implemented using
Multiple-Busses Multiplexer –
Based transfer as shown.
- Connection in this case is very
complex (Consists of M busses each
has n signals for M registers with n
bits/register).

Dr. Ibrahim Qamar 32

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Register Transfer Logic RTL
1. Multiple-Busses Multiplexer –Based RT
- This RT supports more than one transfer at a time.

Registers Loads Multiplexer Select Register Transfer

L2 L1 L0 S2 S1 S0
0 0 1 x x 0 R0  R2
1 0 1 1 x 1 R0  R1, R2  R1
0 1 1 x 0 1 R0  R1, R1  R0

Dr. Ibrahim Qamar 33

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Register Transfer Logic RTL
2. Single-Bus Multiplexer –Based RT
- Connects More than one register
using one Bus only as shown.
- Connection in this case is much
simpler than the previous RT
(Consists of one bus with n signals
for M registers with n bits/register).
- It supports one transfer only at a
time (more than one transfer using
the same source are possible)

Dr. Ibrahim Qamar 34

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Register Transfer Logic RTL
2. Single-Bus Multiplexer –Based RT

Registers Loads Multiplexer Register Transfer

Select
L2 L1 L0 S1 S0
0 0 1 1 0 R0  R2
1 0 1 0 1 R0  R1, R2  R1
Not Possible R0  R1, R1  R0

Dr. Ibrahim Qamar 35

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Register Transfer Logic RTL
3. Single-Bus Tri-State RT
- Connects More than one
register using one Bus only
as shown.
- Tri-State Registers as
shown are required for this
transfer.
- It is the simplest RTL
(Consists of one bus with n
signals for M registers
with n bits/register). No
additional logic is required
Dr. Ibrahim Qamar 36
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Register Transfer Logic RTL
3. Single-Bus Tri-State RT
- It supports one transfer only at a time (more than
one transfer for the same source are possible)
- Each Tri-state Register has two control signals L
to load i/p and E to enable o/p of the register.
- L and E for each register are not allowed to be
active simultaneously.
Registers Loads Multiplexer Select Register Transfer
L2 L1 L0 E2 E1 E0
0 0 1 1 0 0 R0  R2
1 0 1 0 1 0 R0  R1, R2  R1
Not Possible R0  R1, R1  R0
Dr. Ibrahim Qamar 37
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Memory Transfer
2N * M bits
Memory Pin Configuration
RAM
The Following pins is
essential for 2N * M Address (N pins) A0 – AN-1
bits RAM memory
.chips D0 – DM-1 Data (M pins)
1. Address Pins
Used to select one of 2N
locations or words in the
memory chip
2. Data Pins
Used to receive data during Write operations or to output data
during Read operations. The number of pins of data is M
(Word size)
Dr. Ibrahim Qamar 38
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Memory Transfer
Memory Pin Configuration 2N * M bits
RAM
3. CS# (Chip Select) Pin
Used to activate the Address (N pins) A0 – AN-1
chip for read or
write operations. Chip Select
#CS D0 – DM-1 Data (M pins)
4. OE# (Output Output Enable
Enable) Pin #OE
Write Enable
Used to activate data for #WE
read operations.

5. WE# (Write Enable) Pin

Used to activate data for write operations. This pin is not found in the
ROM Chips.
Dr. Ibrahim Qamar 39
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Memory Transfer
- According to the memory configuration, Memory Transfer
requires the following signals:
 Address to locate the required memory word during
memory transfer.
R or W signal to identify the direction of the transfer
from (R) or to (W) memory.
Data to be transferred from memory to the Processor,
in case of Read or from Processor to memory, in case of
Write.

Dr. Ibrahim Qamar 40

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Memory Transfer
Microprocessor
Address
MAR

MDR Data Memory

Unit

Read
Control
Internal Write
Bus

Dr. Ibrahim Qamar 41

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Memory Transfer
- The Processor interfaced to the memory should have the
following hardware :
 Memory Address Register (MAR) to hold and out the
memory address during memory operations.
Control Unit to generate the R or W signals.
Memory Data Register to hold the data to be sent to
memory during Write cycles ,or to receive data from
memory during Read cycles.
-Memory transfers are described as follows:
 For Read R: MBR ← M[MAR]
 For Write W: M[MAR] ← MBR

Dr. Ibrahim Qamar 42

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Memory Transfer (More than one address and data Registers)

Address Data Write

S1 S0 Bus Bus En S1 S0
Decoder 0 2:4 2:4 Decoder 1
3 2 1 0 0 1 2 3
Enn A0 B0 En
L
EnLoad
En A1 B1 En
L

En A2 B2 En
L

B3 En
En A3
L
0 1 2 3
2:4 Decoder 2
En S1 S0
CPU Read
Dr. Ibrahim Qamar 43
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Memory Transfer
- Memory transfer for the previous configuration can also be
described by Memory Transfer notation as follows:
 To Read in register B0 using A2 as memory address:
R: B0 ← M[A2]
 The R, W and Decoder Signals required are:
R W S10 S00 S11 S01 S12 S02 = 1 0 1 0 x x 0 0
 To Write contents of B1 in Memory using A3 as Address:
W: M[A3] ← B1
 The Signals required for this transfer are:
R W S10 S00 S11 S01 S12 S02 = 0 1 1 1 0 1 x x
-It is clear that the Memory or register transfer circuits
implement the required transfer using electrical signals
Dr. Ibrahim Qamar 44
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Register File
- It is a small memory consists
of many registers (e.g 4, 8,
16 or 32 registers).
- It has one input Bus and one
or two output Buses.
- The input bus has WE signal
to enable write and address
signals to select the register
to write in
- Each output bus has RE signal and address signals to select the
register to read from.

Dr. Ibrahim Qamar 45

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Register File
- The Register file Shown previously has:
 8-bit input Bus (In) with WE signals and 2 address lines
WA1 and WA0.
 8-bit 2 output Buses (Port A and Port B) with 2 Read
enable signals RAE and RBE and 2 group of address lines
RAA1 RAA0 address signals for Port A and RBA1 RBA0
address signals for Port B.
- A single Register can have 1
input port and two output
ports as shown.

Dr. Ibrahim Qamar 46

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Register File
- The figure
shown shows
the internal
structure of 4
* 8 register
file with 8-bit
1 input port
and 8-bit 2
output ports.

Dr. Ibrahim Qamar 47

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Datapath
- The Datapath circuit is used for
performing operations involving multiple
steps.
- The datapath is responsible for the
manipulation of data.
- It consists of the following:
1. Functional units such as adders,
shifters, multipliers, ALUs, and
comparators.
2. Registers and other memory elements
for the temporary storage of data.

Dr. Ibrahim Qamar 48

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Datapath
- It consists of the following:
3. Buses, multiplexers, and tri-state buffers for the transfer of
data between the different components of the datapath.
- The Datapath circuit generates Status signal to a control unit.
- The Control Units generates the different control signals
required to control the datapath.

Dr. Ibrahim Qamar 49

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Example of a Dedicated Datapath
Design a dedicated datapath to implement the following
program (or algorithm) assuming 4-bit data.

Dr. Ibrahim Qamar 50

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Example of a Dedicated Datapath
- The required Datapath is implemented as follows:
 Each variable is represented by a 4-bit register (in this
example we need 2 registers for A and B variables).
 The INPUT statement is implemented by activating the
Load signal of the loaded variable register. (In this example
INPUT A)
 The output statement is implemented by activating the
Enable signal of the output variable register or by enable
the tri-state buffer controlling it (In this example OUTPUT
B)
 The testing conditions is considered as Status signal (In this
example A = 5).
Dr. Ibrahim Qamar 51
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Example of a Dedicated Datapath
The datapath required for implementing this algorithm is as
shown:

Dr. Ibrahim Qamar 52

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Example of a Dedicated Datapath
The control words required for this algorithm are given in the
following table. The table also gives the values of the
controlling signals required to implement each control word.

Dr. Ibrahim Qamar 53

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Another example of a Dedicated Datapath
Design a dedicated datapath to implement the following
algorithm) assuming 8-bit data.

Dr. Ibrahim Qamar 54

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Another example of a Dedicated Datapath
- The required Datapath is implemented the same way as the
previous example , but this algorithm needs an adder to be
added to the datapath to perform the addition operations.

Dr. Ibrahim Qamar 55

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Another example of a Dedicated Datapath
The datapath required for implementing this algorithm is as
shown:

Dr. Ibrahim Qamar 56

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Another example of a Dedicated Datapath
The control words required for this algorithm are given in the
following table. The table also gives the values of the
controlling signals required to implement each control word.

Dr. Ibrahim Qamar 57

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

General Datapath
- A general datapath is required to implement any algorithm.
- It consists of a group of registers (may be Register file) and an
ALU connected together through one or more buses.
- It also has an input data bus and output data bus controlled by
an enable signal.
- The figure shown in the next slide shows a general datapath
with a 4 * 8 register file, an ALU and a shifter.
- The Operations of the 8-bit ALU and shifter are given in the
tables given in the next slides.

Dr. Ibrahim Qamar 58

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Another example of a Dedicated Datapath

Dr. Ibrahim Qamar 59

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

General Datapath Example
Implement the following algorithm using the general datapath
given before.

Dr. Ibrahim Qamar 60

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

General Datapath example Solution
- In this example the shifter is not needed, so the Pass-through
operation of the shifter is used.
- This algorithm needs 2 registers , R0 for the Sum variable and
R1 for the variable n.
- The Sum (R0) is initialized to 0 by performing subtracting the
Sum itself.
- The control words required for this algorithm are given in the
table given on the next slide .
- Each control word in this table takes one clock time to be
performed.

Dr. Ibrahim Qamar 61

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

General Datapath example Solution
- The 1st and 2nd control words are executed only once at the
beginning of the algorithm and the 5th control word is executed
at the end of the algorithm .
- The 3rd and 4th control words will be executed n times.

Dr. Ibrahim Qamar 62

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

General Datapath example Solution
- The address lines, the enable
signals of the RF, the ALU,
shifter and the multiplexer
control signals are asserted as
shown in the previous table to
perform the required operation of
each control word.
- The Status signal (n ≠ 0) is tested
at the multiplexer output bus
during saving the value of the
variable n.

Dr. Ibrahim Qamar 63

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Control Unit
- The datapath shown on the previous examples require many
signals to control the execution of the different control words.
- These signals must be generated during the execution of each
control word .
- These control words are executed sequentially and some of
them are executed once and others are executed many times in
loops.

Dr. Ibrahim Qamar 64

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Control Unit
- A Control unit is required to generate the control signals
required by the control words. This control unit is basically a
sequential circuit uses the status signals of the datapath as
inputs.
- The control unit is designed by drawing the state diagram by
representing each control word by a state according to the
algorithm and design the sequential circuit satisfying this state
diagram.
- The control units of the examples given before will be designed
next

Dr. Ibrahim Qamar 65

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Control Unit Design
Design the control unit of the datapath of the following
algorithm. (the datapath is designed before as an example).

 The datapath and control words required for this

algorithm are given again in the next slide with the
values of the control signals required for each control
word.
Dr. Ibrahim Qamar 66
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Control Unit Design

Dr. Ibrahim Qamar 67

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Control Unit Design
 The state diagram of the
control circuit of this
datapath is as shown.
 The state diagram has 4
states , one for each
control word.
 The input of the control
circuit is the condition (A
= 5) or not
Complete the design of the sequential
s circuit described by
this diagram. The outputs of this circuit are the inputs of
the datapath
Dr. Ibrahim Qamar 68
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Control unit for General Datapath Example
Design the control unit of the following algorithm using
the general datapath given before.

 The control words required for this algorithm are given

again in the next slide with the values of the control
signals required for each control word.
Dr. Ibrahim Qamar 69
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Control unit for General Datapath Example

 The comparator required to get the status signal of this

algorithm and the location of the test is shown next.
Many position can be used to get the status signal. The
location of the test signal affects the number of states of
the state diagram. The best position is that shown in the
next slide.
Dr. Ibrahim Qamar 70
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Control unit for General Datapath Example
 The state diagram required
for the control unit of this
algorithm is given in the
next slide. The state table
for this state diagram is also
given next in (b).
 The transition table is also
given in(c). Using 3 D flip
flops to implement this
circuit, the transition table
becomes the excitation
table for this circuit.
Dr. Ibrahim Qamar 71
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Dr. Ibrahim Qamar 72

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Control unit for General Datapath Example
 The K-map of the 3 D-flip-flop inputs (D1, D2 and D3)
for this circuit are given in the next slide.
 Using these maps the Boolean functions of D1, D2 and
D3 are obtained as follows:

D0 = Q2'Q1Q0' + Q2'Q0'Start
D1 = Q2'Q1Q0' + Q2'Q0(n ≠ 0)
D2 = Q2Q1'Q0' + Q2'Q0(n ≠ 0)'

Where Q2, Q1 and Q0 are the output of the flip-flops D2, D1

and D0 respectively, (n ≠ 0) is the status signal of the circuit
and Start is the start signal of the algorithm.
Dr. Ibrahim Qamar 73
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Dr. Ibrahim Qamar 74

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Control unit for General Datapath Example
 The truth table of the required outputs of the control
unit given from the control word table is shown. The
inputs used in this table are the flip-flop outputs Q2,
Q1 and Q0.

Dr. Ibrahim Qamar 75

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Control unit for General Datapath Example
 The Boolean functions of the 16 outputs given in the
previous truth table can be obtained using the K-Map.
 These functions are:
IE = Q2'Q1'Q0 RBA1 = 0
WE = Q2' RBA0 = Q2'Q1Q0'
WA1 = 0 ALU2 = Q2'Q0' + Q2'Q1
WA0 = Q2'Q0 ALU1 = Q2'Q1Q0
RAE = Q2'Q1 + Q1'Q0' ALU0 = Q2'Q1'Q0' + Q2'Q1Q0
RAA1 = 0 SH1 = 0
RAA0 = Q2'Q1Q0 SH0 = 0
RBE = Q2'Q0' OE = Q2Q1'Q0‘

The complete circuit of the control Unit for this

General datapath is shown in the next slide
Dr. Ibrahim Qamar 76
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Dr. Ibrahim Qamar 77

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Instruction Set Architectures (ISA)
- A simple ISA may consists of 3 major components as follows:
 The Storage Resources
They consist of the registers or the register files given in the
datapath and both instruction and data memory.
 The Instruction Formats
The Format of the instructions gives the way by which the
instruction is encoded. It consists of many fields, each field
represent a component of the instruction (e.g. operation,
parameters of the operation and so on).
 The Instruction Specifications
The instruction specifications specify the basic operations
supported by the machine.
Dr. Ibrahim Qamar 78
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Instruction Set Architectures (ISA)
- The ISA drives the design of the hardware of the processor.
- It provides to the programmer the public interface for the
underlying hardware.
- At the Assembly Language level, mnemonic names are
given to binary patterns expressed by the op-codes to make
them easier to understand and work with.
- A program written in Assembly Language is translated into
Machine Code by a software tool called the Assembler.
- The machine code is the binary encoding of the machine’s
instructions or op-codes.

Dr. Ibrahim Qamar 79

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Instruction Set Architectures (ISA)
- Such a set of op-codes for an ISA can be viewed as the
machine language for that particular architecture.
- The complete list of assembly language instructions and
how to work with them is provided by the developer in the
support manuals of each processor.
- A microprocessor’s instruction set specifies the basic
operations supported by the machine.
- The objectives of such operations are to transfer or store
data, to operate on data and to make decision based upon
the data values or outcome of the operations

Dr. Ibrahim Qamar 80

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Instruction Set Architectures (ISA)
- The Microprocessor instructions can be classified into the
following groups:
 Data Transfer instructions:
 Flow of control instructions
 Arithmetic and Logic instructions
 Special instructions to control the processor's execution

Dr. Ibrahim Qamar 81

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Classifying Instruction Set Architectures

Dr. Ibrahim Qamar 82

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Classifying Instruction Set Architectures
- The Major ISA are classified into 4 classes. Operands in these
architectures may be named explicitly or implicitly. The 4
classes are:
 Stack Architecture:
 Accumulator Architecture
 Register –Memory Architectures
 Register –Register (Load/Store) Architectures
-The Last 2 types of ISA are grouped under General Purposes
Architecture (GPA) because they use a group of general
purposes registers

Dr. Ibrahim Qamar 83

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Classifying Instruction Set Architectures
 Stack Architecture: OP Code
o It is also called Zero- Address instruction Architecture
since the instruction has no address field but Op-Code.
o This type of machines was early used in some
calculators.
o It is suitable for systems with high speed processors with
low complexities.
o It may be used in real-time embedded control system.
o The operands in a stack architecture are implicitly the top
of the stack.

Dr. Ibrahim Qamar 84

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Classifying Instruction Set Architectures
 Stack Architecture:
o They are the best code density (instruction/Kbyte), more
reliable , cost effective and less consuming power due to
simplicity of the system.
o Examples for stack processors are: Burroughs B5000,
WISC CPU/16, Novix NC4016 and Harris RTX 2000.
o A disadvantage for this architecture is the stack which is
the bottleneck of the operand traffic since all operands
are fetched from the stack.

Dr. Ibrahim Qamar 85

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Classifying Instruction Set Architectures
 Stack Architecture:

Dr. Ibrahim Qamar 86

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Classifying Instruction Set Architectures
 Accumulator Architecture OP Code Source
o It is also called One-Address instruction Architecture
since the instruction has one field for the operand address
and the Op-Code field.
o This type of machines was used in earlier processors and
microcontrollers when memory was quite expensive.
o The operand in the accumulator architecture is implicitly
the accumulator.
o The instructions in this architecture are short.
o Disadvantage: Since Accumulator is the only temporary
storage, memory traffic is high.
o Examples for this architecture are: 6800 CPU and 8051
Microcontroller. Dr. Ibrahim Qamar 87
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Classifying Instruction Set Architectures
 Accumulator Architecture

Dr. Ibrahim Qamar 88

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Classifying Instruction Set Architectures
 Register –Memory Architectures
OP Code Destination Source
o It is also called Two-Address instruction Architecture
since the instructions have up to two field for operand
address (one for memory if any and another for a register
or both for registers) and the Op-Code field.
o One of the operand addresses is a source and destination
at the same time.
o This Architecture uses limited number of General
Purposes Registers (GPS)

Dr. Ibrahim Qamar 89

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Classifying Instruction Set Architectures
 Register –Memory Architectures

Dr. Ibrahim Qamar 90

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Classifying Instruction Set Architectures
 Register –Memory Architectures
o In This architecture, some operands may be in memory
and the others are in registers.
o Data can be accessed without a separate loading
instruction first.
o The instructions in this architecture are variable in length.
o Most of the CISC Processors belong to this architecture.
o Execution time of the instructions is variable.
o Examples for this architecture are: Intel x86 processors
and Motorola 68000 processors.

Dr. Ibrahim Qamar 91

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Classifying Instruction Set Architectures
 Register –Register (Load/Store) Architectures
Destination
OP Code Source1 Source2 Source3
o It is also called Three-Address instruction Architecture
since the instructions have up to Three field for operand
address and the Op-Code field.
o This architecture uses large number of General Purposes
Registers (GPR) or a register file with large number of
registers.

Dr. Ibrahim Qamar 92

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Classifying Instruction Set Architectures
 Register –Register (Load/Store) Architectures
o Only the load and store instructions can access the
memory.
o In this case the instruction has two operand only (a
source and a destination). The instructions are simple and
fixed in length.
o All instructions take similar number of clock cycles for
execution.
o The disadvantages of this architecture are higher
instruction counts and waste memory bits.

Dr. Ibrahim Qamar 93

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Classifying Instruction Set Architectures
 Register –Register (Load/Store) Architectures
o Examples for this architecture are: MIPS, Power PC and
ARM processors.
o Most of the RISC (Reduced Instruction Set Computers)
are classified under this architecture.

Dr. Ibrahim Qamar 94

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Classifying Instruction Set Architectures
 Memory–Memory Architectures (Not used today)
o In this architecture, all operands are in the memory.
o The instructions employ up to three Addresses.
o Doesn’t waste registers as temporary storage.
o Instruction size is variable and the variations is large
compared with the other Architectures.
o An example to this architecture is the VAX Processors

Dr. Ibrahim Qamar 95

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Classifying Instruction Set Architectures

Dr. Ibrahim Qamar 96

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Complex Instruction Set Computers (CISC)
The Goals of CISC Processors is:
- To complete a task using as few lines of instruction as
possible.
- To eliminate the gap (called “Semantic Gap”) between high-
level languages and computer by bringing the hardware up
to the level of the programming language.
- Examples of CISC Processors:
 Intel x86, Motorola 68000, VAX.

Dr. Ibrahim Qamar 97

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Complex Instruction Set Computers (CISC)
Properties of CISC:
 CISC have small number of GPR, large number of
instructions, addressing modes and complex instruction.
 Instructions can operate directly on memory.
 Few lines of machine code per operation due to complexity
of the instructions.
 The CISC Processor hardware is complex due to complexity
of instructions and multiple clock cycles required for
instruction execution.
 The size of encoded Instructions is variable.
 Microprogramming techniques are used to implement the
complicated instructions.
Dr. Ibrahim Qamar 98
Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Complex Instruction Set Computers (CISC)
Advantages of CISC:
 When designing a new processor it is easy to incorporate
the instructions of the predecessors, which means
compatibility between the new processor and the
predecessor.
 Fewer instructions are needed to implement tasks, which
leads to less program storage.
 Simplicity of Compiler Design due to narrow semantic gap.

Dr. Ibrahim Qamar 99

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Complex Instruction Set Computers (CISC)
Disadvantages of CISC:
 The incorporation of older instruction set into newer
generation of processors increases the complexity of the
processor.
 Long instruction execution time.
 Higher power consumption and cost.
 Memory bottleneck is a major problem, due to complex
addressing modes and multiple memory accesses
instruction.

Dr. Ibrahim Qamar 100

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Reduced Instruction Set Computers (RISC)
The Goals of RISC Processors is:
- To produce a simpler and faster set of instructions.
- To simplify the instruction set and adapt it to the real
requirements of user programs.
Examples of RISC Processors:
 PowerPC, MIPS, ARM and Apple iPods, iPhone and iPad.

Dr. Ibrahim Qamar 101

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Reduced Instruction Set Computers (RISC)
Properties of RISC:
 RISC have register file with Large number of GPR, small
number of instructions and addressing modes, and simple
instruction.
 Instructions can execute in one machine cycle or less.
 Instructions cannot operate directly on memory except
Load/Store Instructions.
 The size of encoded Instructions is fixed.
 Complex operations are executed as a sequence of simple
instructions.

Dr. Ibrahim Qamar 102

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Reduced Instruction Set Computers (RISC)
Advantages of RISC:
 RISC Processors use less number of transistors and thus less
power consumption and cheaper.
 The RISC Processor hardware is simpler and easy to design
due to simplicity of the instructions.
 Higher Performance compared with CISC.
Disadvantages of RISC:
 Large Code size hence larger instruction memory size.
 Complex Compiler Design due to wider semantic gap.

Dr. Ibrahim Qamar 103

Cairo University –Faculty of Engineering Embedded System Professional Master

Embedded Systems Architecture

Example for comparing CISC and RISC
An illustrative example with the following assumption:
- A program with 80% of executed instructions being simple
and 20% complex.
- CISC: simple instructions take 4 cycles, complex instructions
take 8 cycles; cycle time is 100 ns.
- RISC: simple instructions are executed in one cycle; complex
operations are implemented as a sequence of instructions (14
instructions on average); cycle time is 100 ns.
- How much time for a program of 1 000 000 instructions?
- CISC: (106*0.80*4 + 106*0.20*8)*10-7 = 0.48 s
- RISC: (106*0.80*1 + 106*0.20*14)*10-7 = 0.36 s

Dr. Ibrahim Qamar 104