Verilog

Overview of Verilog
• Objectives
• Verilog Basics
 Notation
 Keywords & Constructs
 Operators
• Types of Descriptions
 Structural
 Dataflow
• Boolean Equations
• Conditions using Binary Combinations
• Conditions using Binary Decisions
 Behavioral & Hierarchical

Digital Systems: HDL

 Objectives
• To become familiar with the hardware
description language (HDL) approach to
specifying designs
 Be able to read a simple Verilog HDL
description
 Be able to write a simple Verilog HDL
description using a limited set of syntax and
semantics
 Understanding the need for a “hardware view”
when reading and writing an HDL

Digital Systems: HDL

 Introduction
• What is Verilog HDL?

Verilog HDL is a Hardware Description

Language that can be used to model a
digital system at many levels of abstraction:
– Algorithmic-level
– Gate-level
– Switch-level

Digital Systems: HDL

 Where can we use Verilog HDL?

• Verilog is designed for circuit verification and

simulation, for timing analysis, for test analysis
(testability analysis and fault grading) and for
logic synthesis.

• For example, before you get to the structural level

of your design, you want to make sure the logical
paths of your design is faultless and meets the
spec.

Digital Systems: HDL

 Basic Syntax of a Module
module module_name (port_list);
Declarations:
input, output, wire, parameter…..

System Modeling:
describe the system in gate-level, data-flow, or
behavioral style…

endmodule

Digital Systems: HDL

 Verilog Notation - 1
• Verilog is:
 Case sensitive
 Based on the programming language C
• Comments
 Single Line
// [end of line]
 Multiple Line
/*
*/
• List element separator: ,
• Statement terminator: ;

Digital Systems: HDL

 Verilog Notation - 2
• Binary Values for Constants and Variables
 0
 1
 X,x - Unknown
 Z,z – High impedance state (open circuit)
• Constants
 n’b[integer]: 1’b1 = 1, 8’b1 = 000000001, 4’b0101=
0101, 8’bxxxxxxxx, 8’bxxxx = 0000xxxx
 n’h[integer]: 8’hA9 = 10101001, 16’hf1=
0000000011110001
• Identifier Examples
 Scalar: A,C,RUN,stop,m,n
 Vector: sel[0:2], f[0:5], ACC[31:0], SUM[15:0],
sum[15:0]
Digital Systems: HDL
Verilog Keywords & Constructs - 1
• Keywords are lower case
• module – fundamental building block for Verilog
designs
 Used to construct design hierarchy
 Cannot be nested
• endmodule – ends a module – not a statement

• Module Declaration
 module module_name (module_port, module_port, …);
 Example: module full_adder (A, B, c_in,
c_out, S);
Digital Systems: HDL
 Verilog Keywords & Constructs - 2
• Input Declaration
 Scalar
• input list of input identifiers;
• Example: input A, B, c_in;
 Vector
• input[range] list of input identifiers;
• Example: input[15:0] A, B, data;
• Output Declaration
 Scalar Example: output c_out, OV, MINUS;
 Vector Example: output[7:0] ACC, REG_IN, data_out;

Digital Systems: HDL

 Verilog Keywords & Constructs - 3
• Primitive Gates
 buf, not, and, or, nand, nor, xor, xnor
 Syntax: gate_operator instance_identifier (output,
input_1, input_2, …)
 Examples:
and A1 (F, A, B); //F = A B
or O1 (w, a, b, c)
O2 (x, b, c, d, e); //w=a+b+c,x=b+c+d+e

Digital Systems: HDL

 Verilog Operators - 1
• Bitwise Operators
~ NOT
& AND
| OR
^ XOR
^~ or ~^ XNOR
• Example: input[3:0] A, B;
output[3:0] Z ;
assign Z = A | ~B;

Digital Systems: HDL

 Verilog Operators - 2
• Arithmetic Operators
+, -,
• Logical & Relational Operators
!, &&, | |, = =, !=, >=, <=, >, <
• Concatenation & Replication Operators
{identifier_1, identifier_2, …}
{n{identifier}}
 Examples: {REG_IN[6:0],Serial_in},
{8 {1’b0}}

Digital Systems: HDL

Digital Systems: HDL
 Structural/Gate-Level Modeling
Systems structure can be described using Build-in gates or
pre-built modules.
Basic syntax is :

gate-type #delay instance1_name(outputs.., inputs.. ),

:
:
instance6_name(outputs.., inputs.. );

pre-built module module_instance1(output…,inputs..);

Digital Systems: HDL

 Structural Verilog
• Circuits can be described by a netlist as a text alternative to a
diagram - Example (See Figure):
module fig519s (A0, B0, C0, C1, S0);
input A0, B0, C0;
output C1, S0;
//Seven internal wires needed
wire[1:7] N;
//Ports on primitive gates listed output port first
not G1 (N[3],C0), G2 (N[5],N[2]), G3 (N[6],N[3]);
nand G4 (N[1],A0,B0);
nor G5 (N[2],A0,B0), G6 (C1,N[2],N[4]);
and G7 (N[4],N[1],N[3]), G8 (N[7],N[1],N[5]);
xor G9 (S0,N[6],N[7]);
endmodule
Digital Systems: HDL
 Example: A 4 to1 Multiplexer
module Mux4_1 (Z, D,S); D3 T3

output Z; T2
D2
input [3:0] D;
D1 T1
input [1:0] S;
wire S0b, S1b, T0, T1, T2, T3; T0
D0

S0
not #5 inv0(S0b, S[0]),
inv1(S1b, S[1]); S1
and #10 and0(T0, D[0], S1b, S0b),
and1(T1, D[1], S1b, S[0]),
and2(T2, D[2], S[1], S0b),
and3(T3, D[3], S[0], S[1]);
or #10 or1(Z, T0,T1,T2,T3);
endmodule

Digital Systems: HDL

 Data-flow Modeling
• The basic mechanism used to model a
design in the dataflow style is the
continuous assignment.
• In a continuous assignment, a value is
assigned to a net.
• Syntax:
assign #delay LHS_net = RHS_expression;

Digital Systems: HDL

 Dataflow Verilog
• Circuit function can be described by assign statements using
Boolean equations (See Figure):
module fig519d (A0, B0, C0, C1, S0);
input A0, B0, C0;
output C1, S0;
wire[1:2] N;
assign N[1] = ~(A0 & B0); /*Note: Cannot write ~& for
NAND */
assign N[2] = ~(A0 | B0);
assign C1 = ~((N[1] & ~C0) | N[2]);
assign S0 = (~N[2] & N[1])^(~(~C0));
endmodule
Digital Systems: HDL
 Example: 2 to 4 Decoder
module Decoder 2_4(A,B,EN,Z); Z[0]
A
Input A,B,EN; Z[1]
output [0:3] Z;
B Z[2]
wire Ab, Bb;
assign #1 Ab=~A; EN Z[3]
assign #1 Bb=~B;
assign #2 Z[0]=~(Ab & Bb & EN);
assign #2 Z[1]=~(Ab & B & EN);
assign #2 Z[2]=~(A & Bb & EN);
assign #2 Z[3]=~(A & B & EN);
endmodule

Digital Systems: HDL

 Behavioral Modeling
• Designer describes the behavior of the
circuit.

• Structured procedures: always, initial,

blocking, non-blocking, delay, if..else.,
case, casex, casez, while, for, etc…

Digital Systems: HDL

 Behavioral & Hierarchical Verilog
• Circuit function can be described by assign statements at higher
than the logic level :
module addsub (A, B, R, sub) ;
input [3:0] A, B ;
output [3:0] R ;//See Fig. 5-18 for carry out
input sub ;
wire [3:0] data_out;
add A1 (A, data_out, sub, R);
M1comp C1 (B, data_out, sub);
endmodule

Digital Systems: HDL

 Behavioral & Hierarchical Verilog
module add (X, Y, C_in, S);
input [3:0] X, Y;
input C_in;
output [3:0] S;
assign S = X + Y + {3'b0, C_in};
endmodule
module M1comp (data_in, data_out, comp);
input[3:0] data_in;
input comp;
output [3:0] data_out;
assign data_out = {4{comp}} ^ data_in;
endmodule
Digital Systems: HDL
 References
Verilog HDL: A Guide to Digital Design and
Synthesis by Samir Palnitkar

Digital Systems: HDL