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CH05 Internal Memory Technology

This chapter discusses internal computer memory. It describes semiconductor memory types like dynamic RAM (DRAM), static RAM (SRAM), and read-only memory (ROM). DRAM stores data as charge on capacitors and requires periodic refreshing. SRAM uses flip-flops to store data without refreshing. The chapter also covers memory cell structures, error correction techniques like Hamming codes, and advanced DRAM organizations. Key topics include memory organization, modules, interleaving, soft/hard errors, and error correcting codes. Homework problems focus on memory cell operation, types of ROM, error correction codes, and DRAM organizations.

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38 views

CH05 Internal Memory Technology

This chapter discusses internal computer memory. It describes semiconductor memory types like dynamic RAM (DRAM), static RAM (SRAM), and read-only memory (ROM). DRAM stores data as charge on capacitors and requires periodic refreshing. SRAM uses flip-flops to store data without refreshing. The chapter also covers memory cell structures, error correction techniques like Hamming codes, and advanced DRAM organizations. Key topics include memory organization, modules, interleaving, soft/hard errors, and error correcting codes. Homework problems focus on memory cell operation, types of ROM, error correction codes, and DRAM organizations.

Uploaded by

danchoigavip
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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+

William Stallings
Computer Organization
and Architecture
9th Edition
+
Chapter 5
Internal Memory
+
Memory Cell Operation
Semiconductor Memory Types

Table 5.1 Semiconductor Memory Types


+
Dynamic RAM (DRAM)

 RAM technology is divided into two technologies:


 Dynamic RAM (DRAM)
 Static RAM (SRAM)

 DRAM

 Made with cells that store data as charge on capacitors

 Presence or absence of charge in a capacitor is interpreted as a binary 1


or 0

 Requires periodic charge refreshing to maintain data storage

 The term dynamic refers to tendency of the stored charge to leak away,
even with power continuously applied
+
Dynamic
RAM
Structure

Figure 5.2a
Typical Memory Cell Structures
+
Static RAM
(SRAM)
 Digital device that uses the same logic
elements used in the processor

 Binary values are stored using


traditional flip-flop logic gate
configurations

 Will hold its data as long as power is


supplied to it
+
Static
RAM
Structure

Figure 5.2b
Typical Memory Cell Structures
SRAM versus DRAM
SRAM
 Both volatile
 Power must be continuously supplied to the memory to
preserve the bit values

 Dynamic cell
Simpler to build, smaller
DRAM

 More dense (smaller cells = more cells per unit area)


 Less expensive
 Requires the supporting refresh circuitry
 Tend to be favored for large memory requirements
+  Used for main memory

 Static
 Faster
 Used for cache memory (both on and off chip)
+
Read Only Memory (ROM)
 Contains a permanent pattern of data that cannot be changed or
added to

 No power source is required to maintain the bit values in memory

 Data or program is permanently in main memory and never needs to


be loaded from a secondary storage device

 Data is actually wired into the chip as part of the fabrication process
 Disadvantages of this:
 No room for error, if one bit is wrong the whole batch of ROMs must be
thrown out
 Data insertion step includes a relatively large fixed cost
+
Programmable ROM (PROM)

 Less expensive alternative

 Nonvolatile and may be written into only once

 Writing process is performed electrically and may be performed by


supplier or customer at a time later than the original chip fabrication

 Special equipment is required for the writing process

 Provides flexibility and convenience

 Attractive for high volume production runs


Read-Mostly Memory

Flash
EPROM EEPROM
Memory
Electrically erasable
programmable read-only Intermediate between EPROM
Erasable programmable read-
memory and EEPROM in both cost and
only memory
functionality

Can be written into at any time


without erasing prior contents
Uses an electrical erasing
Erasure process can be
technology, does not provide
performed repeatedly
Combines the advantage of byte-level erasure
non-volatility with the
flexibility of being updatable in
place
Microchip is organized so that
More expensive than PROM
a section of memory cells are
but it has the advantage of the
More expensive than EPROM erased in a single action or
multiple update capability
“flash”
Typical 16 Mb DRAM (4M x 4)
Chip Packaging
Figure 5.5

256-KByte
Memory
Organization

+
1MByte Module Organization
Interleaved Memory
Composed of a collection
of DRAM chips

Grouped together to
form a memory bank
Each bank is independently
able to service a memory read
or write request
K banks can service K requests
simultaneously, increasing memory
read or write rates by a factor of K

If consecutive words of memory are


stored in different banks, the transfer
of a block of memory is speeded up
+
Error Correction
 Hard Failure
 Permanent physical defect
 Memory cell or cells affected cannot reliably store data but become stuck at 0 or
1 or switch erratically between 0 and 1
 Can be caused by:
 Harsh environmental abuse
 Manufacturing defects
 Wear

 Soft Error
 Random, non-destructive event that alters the contents of one or more memory
cells
 No permanent damage to memory
 Can be caused by:
 Power supply problems
 Alpha particles
Error Correcting Code Function
+
Hamming
Error
Correcting
Code
+ Layout of Data Bits and Check Bits
Check Bit Calculation
+
Hamming SEC-DED Code
+ Summary Internal
Memory
Chapter 5

 Semiconductor main memory


 Hamming code
 Organization
 DRAM and SRAM  Advanced DRAM organization
 Types of ROM  Synchronous DRAM
 Chip logic  Rambus DRAM
 Chip packaging  DDR SDRAM
 Module organization  Cache DRAM
 Interleaved memory
 Error correction
 Hard failure
 Soft error
+ Key terms Chapter 5

 semiconductor memory  error correcting code (ECC)


 nonvolatile memory  error correction
 read-mostly memory  syndrome
 read-only memory (ROM)  Hamming code
 programmable ROM (PROM)  hard failure
 erasable programmable ROM (EPROM)  soft error
 electrically erasable programmable  single-error-correcting (SEC) code
ROM (EEPROM)  single-error-correcting, double-error-
 dynamic RAM (DRAM) detecting (SEC-DED) code
 static RAM (SRAM)
 flash memory
 volatile memory
+ Homework
Chapter 5

 5.2
 5.3
 5.6
 5.7
 5.10-14

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