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Ece221 4

This document covers combinational logic circuits and Boolean algebra. It discusses sum-of-products (SOP) and product-of-sums (POS) forms, simplifying logic circuits using algebraic and Karnaugh map methods, exclusive-OR and exclusive-NOR gates, enable/disable circuits, and characteristics of digital integrated circuits. Example circuits are provided to illustrate key concepts.

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24 views23 pages

Ece221 4

This document covers combinational logic circuits and Boolean algebra. It discusses sum-of-products (SOP) and product-of-sums (POS) forms, simplifying logic circuits using algebraic and Karnaugh map methods, exclusive-OR and exclusive-NOR gates, enable/disable circuits, and characteristics of digital integrated circuits. Example circuits are provided to illustrate key concepts.

Uploaded by

jfterpstra
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Chapter 4

4-1.Sum-of-product (SOP) form for a Boolean


Expression
• Useful in simplification and design
• Two or more AND terms ORed together
– Ex: ABC+ABC, AB+ABC+CD+D,
– the inversion sign cannot cover more than one variable ABC
• Alternate form: Product-of-Sums (POS)
– Another general form : (A+B+C)(A+C)
– will not be used often in this course
• Review Questions
– Which of the following is in SOP form?
• AB+CD+E AB(C+D) (A+B)(C+D+F) MN  PQ
– Repeat the above for POS form
4-2.Simplifying Logic Circuits
• First obtain one expression for the circuit, then try to simplify.
• Example:

• Two methods for simplifying


– Algebraic method (use Boolean algebra theorems)
– Karnaugh mapping method (systematic, step-by-step approach)
4-3 Algebraic Simplification
• Put the original expression into SOP form by repeated
application of DeMorgan theorems
• Once in SOP form, check for common factors and factor
whenever possible.
• Example:
4-4 Combinational Logic Circuit Design
(concept introduced by example)

A logic circuit having 3 inputs, A, B, C will have its output HIGH


only when a majority of the inputs are HIGH.
A B C x
0 0 0 0
Step1. Set up the truth table
0 0 1 0
0 1 0 0
0 1 1 1  ABC
1 0 0 0
Step 2. Write the AND term for
1 0 1 1  ABC
each case where the output 1 1 0 1  ABC

is a 1. 1 1 1 1  ABC
Step 3. Write the SOP form the output
Step 4. Simplify the output expression

x  ABC  A BC  AB C  ABC
x  ABC  ABC  A BC  ABC  AB C  ABC  BC  AC  AB
Step 5. Implement the circuit

x = BC + AC + AB
4-5 Karnaugh Map (K Map) Method
K Map shows the relationship between inputs and outputs. The
horizontally and vertically adjacent squares differ only in one variable.
Looping is a process combining the squares which contain 1s. The
output expression can be simplified by looping.
FIGURE 4-12 Examples of looping pairs of adjacent 1s.
FIGURE 4-13 Examples of looping groups of four 1s (quads).
4-5 Karnaugh Map (K Map) Method cont.
FIGURE 4-14 Examples of looping groups of eight 1s (octets).
• Summary :When a variable appears in both complemented and uncomplemented
form within a loop, that variable is eliminated from the expression. Variables that
are the same for all squares of the loop must appear in the final expression.

• Complete Simplification Process


1. Construct the K map and place 1s and 0s in the squares according to the truth table.
2. Loop the isolated 1s which are not adjacent to any other 1s. (single loops)
3. Loop any pair which contains a 1 adjacent to only one other 1. (double loops)
4. Loop any octet even if it contains one or more 1s that have already been looped.
5. Loop any quad that contains one or more 1s that have not already been looped, making
sure to use the minimum number of loops.
6. Loop any pairs necessary to include any 1s that have not yet been looped, making sure to
use the minimum number of loops.
7. Form the OR sum of all the terms generated by each loop.
4-5 Karnaugh Map (K Map) Method cont.
FIGURE 4-15 Examples 4-10 to 4-12.
4-5 Karnaugh Map (K Map) Method cont.
“Don’t-Care” Conditions are certain input conditions for which there
are no specified output levels.

FIGURE 4-18 “Don’t-care” conditions should be changed to either 0 or 1 to


produce K-map looping that yields the simplest expression.
4-5 Karnaugh Map (K Map) Method cont.

Summary
Compared to the algebraic method, the K-map process is a more
orderly process requiring fewer steps and always producing a
minimum expression.
For the circuits with large numbers of inputs (larger than four),
other more complex techniques are used.
4-6 Exclusive-OR and Exclusive-NOR Circuits
Exclusive-OR (XOR) produces a HIGH output whenever the two
inputs are at opposite levels.
Exclusive-NOR (XNOR) :
Exclusive-NOR (XNOR) produces a HIGH output whenever the two
inputs are at the same level.
XNOR gate may be used to simplify circuit implementation.
4-7 Parity Generator and Checker
FIGURE 4-25 XOR gates used to implement the parity generator and the parity
checker for an even-parity system.
4-8 Enable/Disable Circuits
FIGURE 4-26 Four basic gates can either enable or disable the passage of an
input signal, A, under control of the logic level at control input B.
4-8 Enable/Disable Circuits cont.
Example 4-21(Fig.a): Design a logic circuit that will allow a signal to pass
to the output only when control inputs B and C are both HIGH;
otherwise , the output will stay LOW.

Example 4-22(Fig.b): Design a logic circuit that will allow a signal to


pass to the output only when one , but not both, of the control inputs are
HIGH; otherwise , the output will stay LOW.
4-9 Basic Characteristics of Digital ICs
• Digital ICs (chips): a collection of resistors, diodes and transistors
fabricated on a single piece of semiconductor materials called
substrate.
• Dual-in-line package (DIP) is a common type of packages.
4-9 Basic Characteristics of Digital ICs cont.
•Categorized according to the number of the gates on the substrate:
SSI, MSI, LSI, VLSI, ULSI, GSI
•Categorized according to electric components used:
Bipolar ICs (e.g. TTL family) and Unipolar Ics (e.g. CMOS
family)
FIGURE 4-30 (a) TTL
INVERTER circuit; (b) CMOS
INVERTER circuit. Pin numbers
are given in parentheses.

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