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TEXTIO

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P. VENKATESHWARI
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22 views11 pages

TEXTIO

Uploaded by

P. VENKATESHWARI
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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TEXTIO

FILE
• VHDL provides a std package that can be used to read or write lines
from or to a file.
• Files are frequently used with test benches to provides a source of
test data and to provide storage for test results.
• File is declared within architecture, process, or package. The file is
opened when simulator starts and it closes when exit from it.
• File is also declared in subprogram.
Syntax
File file_name: file_type open [mode] is “file_pathname”;

File test_data: Open read_mode is “c:\test_circuit\test.dat”;


modes:-
1. read_mode
2. Write_mode
3. Append_mode
Modes
• Read_mode: successive elements in the file can be read using the
read procedure
• Write_mode: a new empty file is created by the host computer file
system and successive data file can be written in the file.
• Append_mode: successive data elements can be written to an existing
file
Type
• A file can contain only one type of data objects

Syntax:
Type file_name is file of data_type;

Type my_file is file of bit_vector;


Each file type has an implicit end file function
Endfile(file_name)
TEXTIO data types
• LINE type is a text buffer used to interface VHDL I/O and the file.
• Variable type
• A file of type TEXT is used to read characters. TEXTIO package
contains procedure for reading lines of text from a file of type text
and for writing lines of text to a file.
Reading vectors from a text file
• Procedure to read the values from the file
• Readline( Filename, linename): reads a lines from the file
“filename” and stores it in a variable of type “line” called
“linename”
• Read (linename, variablename): reads an element from the line
“linename” and stores it to “variablename”
Cont…
• First open the file
• Read whole lines of the text from the file
• Then disassemble the text line into its elements and convert that
elements into a VHDL types
Program
Use std.textio.all;

Architecture arctbench of tbench is


File datainfile : Open read_mode is “C:\input\datainfile.dat”;
--type
Begin
process
--file variable
variable vdatainline:line;
variable vdatain: bit_vector(7 downto 0);
begin
for I in 0 to 7 loop
wait until (clk’event and clk=‘1’);
readline (datainfile, vdatainline);
read(vdatainline,vdatain);
datainout<= to_stdlogicvector(vdatain);
End loop;
Writing vectors into a text file
• The write procedure used to write one or more times to write data to
line buffer and then the call writeline to write the line of data to a file

• Write(linename, varaiblename): writes an element stored in


“variablename” to the line “linename”
• Witeline(filename, linename): writes a line called “linename” to a file
with object name “filename”.
Program
Process(clk)
Variable vdataout:bit_vector(7 downto 0);
Varaibale vdataoutline :line;
Begin
If (datavalid=‘1’) then
Vdataout:=to_bit vector(dataout);
Write (vadataoutline, vdataout);
Writeline(dataoutfile, vdataoutline);
End if;
End process;

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