8085

MICROPROCESSOR
Definition : Microprocessor
• The word comes from the combination Micro (indicating very
small size) and Processor (process means to manipulate e.g.
certain operations on the numbers)
• The microprocessor is the central processing unit (CPU) of
the computer. It is heart of computer
OR
• A programmable device that takes in numbers, performs on
them arithmetic or logical operations according to the
program stored in memory and then produces other numbers
as a result
Features :

• 8 bit microprocessor(8085 microprocessor can read or write or

perform arithmetic and logical operations on 8-bit data at time)
• It has 8 data lines and 16 address lines hence capacity is 216 =
64 kB of memory
• Clock frequency is 3 MHz
• It requires +5V power supply.
• It is a single chip NMOS device implemented with 6200
transistors.
• It provides 74 instructions with five addressing modes.
• It provides 5 hardware interrupt and 8 software interrupts.
Simple block diagram of μp-8085
μp consists of 3 main sections
• ALU – Arithmetic & Logic Unit
ALU of 8085 performs 8-bit arithmetic & logical
operations like addition, subtraction, logical AND, logical
OR, logical EX – OR, complement, increment,
decrement, left shift, right shift, rotate left, rotate right,
clear etc. The operations are generally performed with
Accumulator as one of the operands. The result is saved
in accumulator register.
• Timing & Control Unit
This unit works as the brain of the CPU and generates all
the timing and control signals to perform all the internal
& external operations of the CPU.
• Registers – Programmable registers of 8085
• Registers are used by the μp for temporary storage and
manipulation of data and instruction. Data remain in the
registers till they are sent to the memory or I/O device. The
8085 has the following registers
1. One 8-bit accumulator (Acc) i.e., register A
2. Six 8-bit general purpose registers (B,C,D,E,H & L)
3. One 16-bit program counter (PC)
4. One 16- bit stack pointer (SP)
5. Instruction register
6. Temporary register
Functional Block diagram/ Architecture of 8085
Architecture 0f 8085 Cont…
1. ALU 8. Interrupt Control
2. Timing and Control Unit 9.Serial I/O Control
3. General Purpose Registers 10.Address Bus
4. Program Status word/Flag 11. Data Bus
Register
5. Program Counter
6. Stack Pointer
7. Instruction Register and
Decoder
The Registers are of 8-bit & 16-bit size used for different purposes
• A- Accumulator :
• 1. This is a special purpose 8-bit register.
• 2. All the ALU operations are performed with reference to the

contents of Accumulator.
• 3. The final result of an AL – operation is placed in the accumulator.
• 4. Some logical instructions need only one data. It is held in the
accumulator.

• General Purpose Registers: (B, C, D, E, H, L)

• 1. These registers can also used for 16-bit operations in pairs.
• 2. The default register pairs are BC, DE & HL.
• 3. The H-L pair is used to act as memory pointer

*These registers and accumulator are accessible to programmer

Program counter: (PC)
• 1. It is a 16-bit special purpose register.
• 2. It is used to hold the memory address of the next instruction to
be executed.
• 3. It keeps the track of memory address of the instruction in a
program while they are being executed.
• 4. The μp increments the content of the program counter during
the execution of an instruction.

Stack Pointer : (SP)

• 1. It is also a 16-bit special function register.
• 2. It is used to address the top of the stack memory location.
Instruction Register:
• 1. It holds the instruction code / op-code of the instruction

Instruction Decoder & Machine Cycle Encoder Unit:

• This unit decodes the op-code stored in the Instruction
Register (IR) and encodes it for the timing & control
unit to perform the execution of the instruction.

Temporary register W & Z:

• 1. These registers are only used by 8085 and are not available for
the programmer.
F – Flag register : This register indicates the status of the ALU operation.
• Carry (CS):The carry status flag holds carry out of the most significant
bit resulting from the execution of an arithmetic operation If there is a
carry from addition or a borrow from subtraction or comparison, the
carry flag CS is set to 1 otherwise 0

• Zero (Z):The zero status flag Z is set to 1 if the result of an arithmetic

or logical operation is zero For non-zero result it is set to 0

• Sign (S):The sign status flag is set to 1 if the most significant bit of the
result of an arithmetic or logical operation is 1otherwise 0

• Parity (P):The parity status flag is set to 1 when result of the operation
contains even number of 1's It is set to zero when there is odd number
Example:
9
CB
The 8085 Bus Structure
• The 8-bit 8085 CPU (or MPU – Micro Processing Unit)
communicates with the other units using a 16-bit address bus,
an 8-bit data bus and a control bus.
Bus Organisation:
•Data Bus
•Address Bus
•Control Bus
The μp performs the basic four operations
i. Memory Read: Reads data from memory
ii. Memory Write : Writes data into memory
iii. I/O Read: Accepts data from i/p devices
iv. I/O Write: Sends data to o/p devices

All these operations are part of communication process between the CPU and
external devices. These communications are performed with the help of the
above said buses
Address & Data Bus
• Data bus is 8-bit wide and hence, 8-bits of data can be transmitted in parallel
from or to the μp.
• They are bidirectional. These are used to transfer data.
• μp requires a 16-bit wide address bus as the memory addresses are of 16-bit.
• The 8 MSBs of the address are transmitted by the address bus, A-bus (A8 to
A15)pins
• The 8 LSBs of the address are transmitted by the address/data bus, AD-
bus(AD0-AD7)pins
• These address/data bus transmits data and address at different moments. Thus
AD-bus operates in time shared mode. This technique is known as
multiplexing.
• First 8 MSBs of the memory address are transmitted on the A –(address) bus
and 8 LSBs on the AD – (address/data) bus.
• Control Bus:
• These are comprised of various single lines
• They provide the timing and synchronization signals.
• They are individual lines that provide a pulse to indicate an
CPU operation.
• CPU generates specific control signals for every operation it
performs.
Pin Configuration:
Pin Configuration cont…
1) Address Bus (A15-A8 and AD7-AD0):
The microprocessor 8085 has 16 bit address lines from A15-
A8 and AD7-AD0. These lines are used to transfer 16 bit address of
memory as well as 8-bit address of I/O ports.

2) Data Bus (AD0 – AD7):

The lower 8 lines (AD7-AD0) are often called as multiplexed
data lines. They serve dual purpose. They are used to carry 8LSBs
of memory address or I/O port address in 1st clock cycle. And for
data transfer during 2nd and 3rd clock cycle
3)CONTROL LINES:
• RD (O/P) : Read: This is active low signal which indicates that the
selected I/O or memory device is to be read and also is available on the
data bus.
• WR (O/P) : Write: This is active low signal which indicates that the data
on data bus are to be written into a selected memory location.
• IO/ M (O/P) : (Input / Output / Memory): This is used to select either
Input / Output devices or memory operation. When it is high it indicates
an I/O operation and when it is low, it indicates a memory operation.
4)STATUS LINES:
• Status Pins (S1, S0) (O/P) : The microprocessor 8085 has two status pins
as S1, S0 which is used to indicate the status of microprocessor or
operation which is performed by microprocessor.
S1 S0 Operation
0 0 HLT State
0 1 Writing Operation
1 0 Reading Operation
1 1 Opcode fetch Operation
5) ALE (O/P) (Address Latch Enable):
This signal is used primarily to latch the low order address from the multiplexed
bus and generate a separate set of eight address lines A7 – A0
6) READY (I/P): It is used by the μp to sense whether a peripheral is ready to
transfer data or not.
7) HOLD (I/P): This signal indicates that peripheral is requesting the use of the
address and data bus.
8) HLDA (O/P) : This signal acknowledges the HOLD signal.
9) INTR (I/P): It is an interrupt request signal. Among interrupts it has the lowest
priority. When it goes high, the μp suspends its normal execution of the
instructions and attends the interrupt signal. This signal is used by the I/O
devices to transfer the data to the μp.
10) INTA (O/P) : It is an interrupt acknowledgement sent by the μp after INTR is
received.
11)RST 7.5 ,6.5, 5.5 (I/P):Restart interrupts These interrupts transfer the
program control to specific memory location they have higher priorities than the
INTR interrupt among these three the priority order is 7.5 ,6.5 and 5.5
12)TRAP(I/P): This interrupt has the highest priority.
The order of priority of interrupts is
• TRAP(highest priority )
• RST 7.5
• RST 6.5
• RST 5.5
• I NTR (lowest priority)
13)RESET IN (I/P): It resets the program counter to zero it also resets interrupt
enable and HLDA flip flops it does not affect any other flag or register accept
the instruction register.
14)RESET OUT(O/P): It indicates that the CPU is being reset
15)X1,X2 (I/P): These are terminals to be connected to an
external crystal oscillator which drives and internal circuitry of
the μp to produce a suitable clock for the operation of μp
16)CLK(O/P):It is a clock output for a user which can be used for
other digital ICS its frequency is same at which μp operates
17)SID (I/P):It is a data line for serial input. The data on this line
is loaded into the 7th bit of the accumulator when are RIM
instruction is executed
18)SOD(O/P): It is a data line for serial output.The seventh bit of
the accumulator is output on SOD line when SIM instruction is
executed
19)Vcc: +5 volts dc supply
Op-Code & Operands
• Each instruction contains two parts:
• 1. Operation Code (Op-code) – The first part of instruction
which specifies the task to be performed by the computer
is called Op-code.
• 2. Operand – The second part of the instruction is the
data to be operated on and it is called operand

The operand given in the instruction may be in various forms such

as 8-bit or 16-bit data, 8-bit or 16-bit address, internal registers or
Instruction Set
Instructions are broadly classified into two types:
 Based on word size:
• One byte instruction- Opcode only (ADD B,CMA)
• Two byte instruction- Opcode, an operand (MVI B,05H)
• Three byte instruction- Opcode, operand, operand (LXI2400, STA 4500)
 Based on function:
• Data transfer group (MOV A,B; MVI A,32H;MOV C,4500)
• Arithmetic operations (ADD B, SBI 32H,INC D, DEC B)
• Logical operations (ANA B, ORI 05H, RLC, RAR)
• Branching operations (JUMP, JMP, JNZ, JC, CALL, RETURN)
• Machine control instructions (HLT, NOP,EI,DI,SIM,RIM)
• Consider an example for one byte instruction,
ADD B – Add the content of register B to the content of the
accumulator.
The op-code for this instruction is 80H
The binary form of 80H is 10000000 – The first five bits 10000
specify the operation to be performed i.e., ADD operation.
The last three bits 000 are the code for register B

• Consider an example for two byte instruction,

MVI B,05H- Move the data 05 to register B.
The op-code for this instruction is 06,05
• Consider an example for three byte instruction,
LXIH,2400H- Load H-L pair with 2400H
The op-code for this instruction is 21,00,24
The first byte 21 is the op-code for instruction LXIH.
Second byte 00 is the LSBs of the data 2400H(Loaded in
register L)
Third byte 24 is the MSBs of the data 2400H(Loaded in
register H)
Addressing Modes
ADDRESSING MODES: The different techniques to specify data for instructions are called Addressing
Modes.
Thay are as follows -

• Direct (LDA 4500H; STA 7500H; IN 09H; OUT 70H)

• Register (MVI A,05H; LXI B, 20AEH; ADI 05H;ORI

07H)

• Indirect (MOV A, M; MOV M,A; ADD M; ORA M)

• Immediate (MOV A,B ; ADD B; SUB E; ANA C)

• Direct Addressing Mode: In this type the address of the operand
(data) is given in the instruction itself.

Ex: STA 2400H – Store the content of accumulator in the

memory location 2400H

• Here 2400H is the memory address where data is to be stored. It

is given in the instruction itself.
• The 2nd and 3rd bytes of the instruction specify the address of the
memory location.
• Here source of the data is accumulator.
• Register Addressing Mode: In this type the operands (data) are in the
general purpose registers. The opcode specifies the address of the
registers in addition to the operation to be performed.
Ex: MOV A,B – Move the content of register B to register A

• Indirect Addressing Mode: In this type the address of the operand is

specified by a register pair
Ex: LXI H, 2500H – Load H-L pair with 2500H
MOV A, M – Move the content of memory location, whose
address is in H-L pair (i.e., 2500H) to the
accumulator.
HLT – Halt
• Immediate Addressing Mode: In this type the operand (data) is
specified within the instruction itself.
Ex: MVI A,05 – Move the data 05 in register A
• Here 2nd byte specifies data.

• Implicit Addressing Mode: Certain instructions operate on the

content of the accumulator. Such instructions do not require the
address of the operand
• Ex: CMA, RAL, RAR etc
Instruction Set
Based on their function instructions are classified as
follows
• Data transfer group (MOV A,B; MVI A,32H;MOV C,4500)
• Arithmetic operations (ADD B, SBI 32H,INC D, DEC B)
• Logical operations (ANA B, ORI 05H, RLC, RAR)
• Branching operations (JUMP, JMP, JNZ, JC, CALL,
RETURN)
• Machine control instructions (HLT, NOP,EI,DI,SIM,RIM)
Instruction Cycle
• Instruction: An instruction is a command given to the
computer to perform a specified operation on given
data.

• Program: A sequence of instructions to perform a

perticular task is called a program.

• Program and data are stored in the memory.

• The necessary steps that a CPU carries out to fetch an
instruction and necessary data from the memory and to
execute it, constitutes an instruction cycle.

• An instruction cycle consists of a fetch cycle and

execute cycle.

• The steps which are carried out by the CPU to fetch an

op-code (machine code) from the memory constitute a
fetch cycle.
• The time required to fetch an op-code is a fixed slot of
time.
• Time required to execute an instruction is variable.
• The total time required to execute an instruction is
given by
IC = FC + EC
Fetch operation:
• An instruction may be more than one byte long
• The 1st byte of an instruction is its op-code
• The other bytes are data or operand address
• The program counter (PC) keeps the memory address of the next
instruction to be executed.
• In the beginning of the fetch cycle the content of the program counter is
sent to the memory
• The memory places the op-code on the data bus so as to transfer it to
CPU
• The entire operation of fetching an op-code takes 3 clock cycles
• A slow memory may take more time.
Execute Operation
• The op-code fetched from the memory goes to data register (DR) (IR)
Decoder
• Decoder decodes the instruction, after decoding execution begins.
• If operand (data) is in general purpose registers, execution is
immediately performed.
• The time taken in decoding and execution is 1clock cycle.
• If the data is in memory, then CPU has to perform some read
operation to get desired data.
• After receiving data execution is performed.
• Here read cycle is similar to fetch cycle, but the quantity received is
data or address of data instead of op-code.
• In some cases write operation is performed.
• In write operation data is sent from the CPU to the memory or
an o/p device.
• In some cases, this execute cycle involves one or more read or
write or both cycles.
Machine Cycle:
• The steps carried out to perform the operation of accessing memory or I/O
device constitute a machine cycle.
• In machine cycle one basic operation such as opcode fetch, memory read,
memory write, I/O read or I/O write is performed.
• One instruction cycle consists of many machine cycles.
• The op-code of an instruction is fetched in the 1st machine cycle of an
instruction cycle.
• Single byte instructions require only one machine cycle to fetch and
execute the instruction
• Two and three byte instructions require more than one machine cycle.
• Additional machine cycles are required to read data from or to
write data into the memory or I/O devices.
• One sub division of an operation performed in one clock cycle
is called a State or T - state
Timing diagrams:
Definition: The steps carried out in a machine cycle can be represented graphically.
Such a graphical representation is called timing diagram. The timing diagram for
the following basic functions will be discussed.

1. Op-code Fetch cycle(4T or 6T).

2. Memory read cycle (3T)
3. Memory write cycle(3T)
4. I/O read cycle(3T)
5. I/O write cycle(3T)
Timing Diagram for Op-code fetch cycle:
• The μp issues a low IO/M signal to indicate that it wants to make
communication with memory
• It sends out high S0 & S1 signals to indicate that it is going to perform fetch
operation
• During 1st clock cycle T1, the μp sends out the address of memory location
where op-code is available.
• The 8-MSBs of 16 bit memory address is sent through A –bus and 8-LSBs thr’
AD- bus.
• Since AD- bus is needed to transfer data during subsequent clock cycles, it
works in time multiplexed mode.
• It is made free during T2 & T3
• μp sends an address latch enable signal ALE to latch 8-LSBs of the memory
address
• 16-bit memory address is needed by memory to obtain the op-code from the
given memory address.
• During T2 AD-bus becomes ready to carry data.
• In T2 the μp makes RD low.
• Now memory gets op-code from specified memory
location and places it on the data bus.
• During T3, the op-code is placed in instruction register(IR)
• The memory is disabled when RD goes high during T3.
• The fetch cycle is completed by T3.
• The op-code is decoded in T4
Timing Diagram for Memory read Cycle:
• In a memory read cycle the μp reads the content of memory location
and places that data either in accumulator or any other register of the
CPU.
• Ex: Consider 2 byte long instruction, MVI A, 05
• This instruction requires two machine cycles M1,M2
• The first machine cycle M1 is to fetch the op-code.
• The second machine cycle M2 is for reading the data.
• IO/M goes low, indicating that the address is for memory.
• S1 & S0 are set to1 & 0 resply for read operation.
• The MSBs of the memory address of the data (05) are sent on A8-A15.
• During T2, 8LSBs of the address is latched and AD0 – AD7 are made
free for data transmission
• RD goes low in T2 to enable the memory for read operation
• Now data is place on data bus.
• During T3 the data enters into the CPU
• In T3, RD goes high and disables the memory.
• This cycle consists of 3-clock cycles
Timing Diagram for I/O read Cycle:
• In an I/O read cycle the microprocessor reads the data
available at an I/P port or I/P device.
• The data is placed in the accumulator.
• An I/O read cycle is similar to memory read cycle.
• The only difference between memory read cycle and I/O
read cycle is that signal IO/M goes high in case of I/O
read.
• It indicates that address on the A- bus is for an input
device.
• In case of I/O device the address is 8 -bits long therefore
address of I/O device is duplicated on both A and AD
• It is 2 byte long.
• It requires 3 machine cycles for execution.
• The first machine cycle is op-code fetch cycle.
• The second machine cycle is memory read cycle to read
the address of the input device.
• Third machine cycle is I/O read cycle to read the data
from the device
Timing Diagram for Memory write Cycle:
• In this cycle, CPU sends data from the accumulator or
any other register to the memory.
• The status signals S1 & S0 are 0 & 1 respectively.
• For write operation WR goes low in T2 indicating that it is
going to perform write operation.
• During T2, the AD – bus is not disabled as it is done in
case of read operation
• Data to be sent out to the memory is placed on the AD –
bus
• When WR goes high in T3, the write operation is
terminated.
Timing Diagram for I/O write Cycle:
• In this cycle, CPU sends data to an I/O port or I/O device from the
accumulator.
• In case of I/O write cycle IO/M goes high indicating that the address
sent out by CPU is for I/O device or I/O port.
• The address of an I/O port or device is duplicated on both A and AD
buses.
• The OUT instruction is used for I/O write operation.
• It is two byte long
• It requires 3 machine cycles.
• 1st machine cycle – op-code fetch
• 2nd machine cycle – memory read cycle for reading I/O device address
• 3rd machine cycle – I/O write cycle for sending data to the I/O device
Eg:
Eg:
PROGRAMMING WITH
8085
8-BIT ADDITION & SUBTRACTION
Program: Program:
MVI A, 04H MVI A, 06H
MVI B, 06H MVI B, 04H
MVI C, 00H MVI C, 00H
ADD B SUB B
JNC LP1 JNC LP1
INR C INR C
LP1: STA 4500H LP1: STA 4500H
MOV A, C MOV A, C
STA 4501H STA 4501H
HLT HLT
8 BIT MULTIPLICATION
MVIA, 00 H
MVIB, 05 H
MVID, 04 H
MVIC, 00 H
*ADD B
JNC #
INR C
# DCR D
JNZ *
STA 9000 H
MOV A, C
STA 9001 H
HLT
8 BIT DIVISION
MVIA, 04 H
MVIB, 02 H
MVIC, 00 H
#SUB B
INR C
JNC #
ADD B
DCR C
STA 9000 H
MOV A, C
STA 9001 H
HLT
16 –BIT ADDITION &SUBTRATION:
Program:
Program:
MVI B, 00 MVI B, 00 H
LXI H, 1111 H LXI H, 2222 H
LXI H, 1111 H
LXI D, 2222 H
MOV A, L
MOV A, L SUB E
ADD E MOV L, A
MOV A, H
MOV L, A SBB D
MOV A, H JNC #
INR B
ADC D
#MOV H, A
JNC # SHLD 9000 H
INR B MOV A, B
STA 9002 H
# MOV H, A HLT
SHLD 9000 H
16 –BIT MULTIPLICATION & DIVISION
Program: Program:
LXI B, 0000 H
LXI B, 0000 H LHLD 9002 H
LHLD C100 H XCHG
LHLD 9000 H
SPHL $INX B
MOV A, L
LHLD C102 H SUB E
XCHG MOV L, A
MOV A, H
LXI H, 0000 H SBB D
@ DAD SP MOV H, A
SBB D
JNC * MOV H, A
JNC $
INX B
DAD D
*DCX D DCX B
SHLD 9100 H
MOV A, D MOV L, C
ORA E MOV H, B
SHLD 9102 H
JNZ @ HLT
To find the greatest between two numbers:
Program
MVI B, 30H
MVI C, 40H
MOV A, B
CMP C
JZ EQU
JC GRT
OUT PORT1
HLT
EQU: MVI A, 01H
OUT PORT1
HLT
Code conversion
• ASCII to decimal
• Decimal to ACSII
• BCD to HEXA
• Hexa to BCD
• Hexa to binary