1-Module - 1 IntroductionOverview of Embedded Systems,-05!01!2024
1-Module - 1 IntroductionOverview of Embedded Systems,-05!01!2024
CPU
Based System
External RAM, ROM, I/O
(No internal RAM, ROM, I/O ports in the CPU)
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Microcontroller
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Microprocessor vs. Microcontroller
Microprocessor Microcontroller
• CPU is stand-alone, RAM, • CPU, RAM, ROM, I/O and
ROM, I/O, timer are separate timer are all on a single chip
• Designer can decide on the • Fixed amount of on-chip
amount of ROM, RAM and I/O ROM, RAM, I/O ports df
ports. dfdfdfdfdfdfdf
• Expansive • Not Expansive
• Versatility • Single-purpose
• General-purpose
• Special Purpose.
4
C based Embedded Systems
• Special purpose computer system usually completely inside
the device it controls
• Has specific requirements and performs pre-defined tasks
• Cost reduction compared to general purpose processor
• Different design criteria
• Performance
• Reliability
• Availability
• Safety
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Embedded Systems Examples
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Examples
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Harvard Architecture
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8051 CPU Operation
1. Features
2. Pin Diagram
3. Block Diagram
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8051 Microcontroller
• Intel introduced 8051, referred as MCS- 51, in 1981.
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Features of 8051
8 bit Processor
4KB Internal ROM
128 Bytes Internal RAM
Four 8 BIT I/O PORTS (32 I/O LINES)
Two 16 Bit Timers/Counters
On Chip Full Duplex UART for Serial Communication
5 Vector Interrupts ( 2 External, 3 Internal - Timer0,Timer1,Serial)
On Chip Clock Oscillator
16 bit Address bus
64k External Code Memory
64k External Data Memory
16-bit program counter to access external Code Memory and
16 bit Data Pointer to access external Data Memory
128 user defined flags
32 General Purpose Registers each of 8 bits
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8051 Family
• The 8051 is a subset of the 8052
• The 8031 is a ROM-less 8051
• Add external ROM to it
• You lose two ports, and leave only 2 ports for I/O operations
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Pin Diagram
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Block Diagram of 8051
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Separate read instructions for external data and code memory.
Pin Description of the 8051
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XTAL1 and XTAL2
• The 8051 has an on-chip oscillator but requires an external crystal to run it
• A quartz crystal oscillator is connected to inputs XTAL1 (pin19) and XTAL2 (pin18)
• The quartz crystal oscillator also needs two capacitors of 30 pF value
• The original 8051 operates at 12 MHZ
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XTAL1 and XTAL2 …..
• If you use a frequency source other than a crystal oscillator, such as a TTL
oscillator:
• It will be connected to XTAL1
• XTAL2 is left unconnected
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RST
• RESET pin is an input and is active high (normally low)
• Upon applying a high pulse to this pin, the microcontroller will reset
and terminate all activities
• This is often referred to as a power-on reset
• Activating a power-on reset will cause all values in the registers to
be lost
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EA’
• EA’, “external access’’, is an input pin and must be connected to Vcc or
GND
• The 8051 family members all come with on-chip ROM to store programs
and also have an external code and data memory.
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PSEN’ and ALE
• PSEN, “program store enable’’, is an output pin
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I/O Port Pins
• The four 8-bit I/O ports P0, P1, P2
and P3 each uses 8 pins.
• All the ports upon RESET are
configured as output, ready to be
used as input ports by the external
device.
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Port 0
• Port 0 is also designated as AD0-AD7.
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Port 1 and Port 2
• In 8051-based systems with no external memory
connection:
• Both P1 and P2 are used as simple I/O.
• In 8051-based systems with external memory
connections:
• Port 2 must be used along with P0 to provide the 16-bit address
for the external memory.
• P0 provides the lower 8 bits via A0 – A7.
• P2 is used for the upper 8 bits of the 16-bit address, designated
as A8 – A15, and it cannot be used for I/O.
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Port 3
• Port 3 can be used as input or output.
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PinPINDescription
TYPE
Summary
NAME AND FUNCTION
Vss I Ground: 0 V reference.
Vcc I Power Supply: This is the power supply voltage for normal,
idle, and power-down operation.
P0.0 - P0.7 I/O Port 0: Port 0 is an open-drain, bi-directional I/O port. Port
0 is also the multiplexed low-order address and data bus
during accesses to external program and data memory.
P1.0 - P1.7 I/O Port 1: Port I is an 8-bit bi-directional I/O port.
P2.0 - P2.7 I/O Port 2: Port 2 is an 8-bit bidirectional I/O. Port 2 emits the
high order address byte during fetches from external
program memory and during accesses to external data
memory that use 16 bit addresses.
P3.0 - P3.7 I/O Port 3: Port 3 is an 8 bit bidirectional I/O port. Port 3 also
serves special features as explained.
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General Block Diagram of 8051
CPU
Bus Serial
OSC 4 I/O Ports
Control Port
TXD RXD
P0 P1 P2 P3
Detailed Block Diagram
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8051 Memory Structure
External
External
60K
64K 64K
SFR
EXT INT 4K
128
EA = 0 EA = 1 Internal
Program Memory
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Internal RAM Structure
Direct
Addressing
Only
SFR [ Special Function
Direct & Registers]
Indirect
Addressing
128 Byte Internal RAM
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Special Function Registers [SFR]
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Program Status Word [PSW]
C AC F0 RS1 RS0 OV F1 P
Carry Parity
Auxiliary Carry User Flag 1
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8051 instructions that affects flag
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128 Byte RAM
• There are 128 bytes of RAM in the 8051.
• Assigned addresses 00 to 7FH
• The 128 bytes are divided into 3 different groups as General Purpose
follows: Area
1. A total of 32 bytes from locations 00 to 1F hex are set aside
for register banks and the stack.
2. A total of 16 bytes from locations 20H to 2FH are set aside BIT Addressable
for bit-addressable read/write memory. Area
3. A total of 80 bytes from locations 30H to 7FH are used for 128 BYTE
read and write storage, called scratch pad. INTERNAL RAM
Reg Bank 3
Reg Bank 2
Register Banks
Reg Bank 1
Reg Bank 0
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8051 RAM with addresses
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8051 Register Bank Structure
Bank 3 R0 R1 R2 R3 R4 R5 R6 R7
Bank 2 R0 R1 R2 R3 R4 R5 R6 R7
Bank 1 R0 R1 R2 R3 R4 R5 R6 R7
Bank 0 R0 R1 R2 R3 R4 R5 R6 R7
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8051 Register Banks with address
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8051 Programming Model
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8051 Stack
• The register used to access the stack is called the SP (stack pointer)
register
• The stack pointer in the 8051 is only 8 bit wide, which means that it can take
value of 00 to FFH
• When the 8051 is powered up, the SP register contains value 07
• RAM location 08 is the first location begin used for the stack by the 8051
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8051 Stack
• Loading the contents of the stack back into a CPU register is called a
POP
• With every pop, the top byte of the stack is copied to the register specified
by the instruction and the stack pointer is decremented once
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Bit Addressable & Byte Addressable
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Single bit Instructions
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Bit Addressable Programming
• Example: Find out to which by each of the following bits belongs. Give the
address of the RAM byte in hex
(a) SETB 42H, (b) CLR 67H, (c) CLR 0FH (d) SETB 28H, (e) CLR 12, (f) SETB 05
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8051 Software Overview
1. Addressing Modes
2. Instruction Set
3. Programming
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8051 Addressing Modes
• The CPU can access data in various ways, which are called addressing
modes
1. Immediate
2. Register
3. Direct
4. Register indirect
5. External Direct
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Immediate Addressing Mode
• The source operand is a constant.
• The immediate data must be preceded by the pound sign, “#”
• Can load information into any registers, including 16-bit DPTR
register
• DPTR can also be accessed as two 8-bit registers, the high byte DPH and
low byte DPL
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Register
• Use registers Addressing
to hold Mode
the data to be manipulated.
• Contrast this with immediate addressing mode, there is no “#” sign in the
operand.
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56
57
• PUSH A is invalid.
• Pushing the accumulator onto the stack must be coded as PUSH 0E0H.
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Register Indirect Addressing Mode
• A register is used as a pointer to the data.
• Only register R0 and R1 are used for this purpose.
• R2 – R7 cannot be used to hold the address of an operand located in RAM.
• When R0 and R1 hold the addresses of RAM locations, they must be
preceded by the “@” sign.
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Register Indirect Addressing Mode
• Write a program to copy the value 55H into RAM memory locations 40H to
41H using (a) direct addressing mode, (b) register indirect addressing
mode without a loop, and (c) with a loop.
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Register Indirect Addressing Mode
• The advantage is that it makes accessing data dynamic rather than static as in
direct addressing mode.
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External Direct
• There are only two commands that use External Direct addressing
mode:
• MOVX A, @DPTR
MOVX @DPTR, A
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8051 Instruction Set
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68
69
70
71
72
Checking an input bit
JNB (jump if no bit) ; JB (jump if bit = 1)
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Switch Register Banks
74
75
76
77
78
79
81
82
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8051 TIMERS
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8051 Timer/Counter
OSC ÷12
C /T 0 TLx THx TFx
(8 Bit) (8 Bit) (1 Bit)
C /T 1
T PIN
INTERRUPT
TR
Gate
INT PIN
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TMOD Register
GATE:
When set, timer/counter x is enabled, if INTx pin is high and TRx
is set.
When cleared, timer/counter x is enabled, if TRx bit set.
C/T*:
When set, counter operation (input from Tx input pin).
When cleared, timer operation (input from internal clock).
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TMOD Register
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TCON Register
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8051 TIMERS
8051 Timer Modes
Timer 0 Timer 1
Mode 0 Mode 0
Mode 1 Mode 1
Mode 2 Mode 2
Mode 3
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TIMER 0
OSC ÷12
C /T 0
TL0 TH0 TF0
C /T 1
T 0 PIN
TR 0 INTERRUPT
Gate
INT 0 PIN
TIMER 0 – Mode 0
13 Bit Timer / Counter
OSC ÷12
C /T 0 TL0 TH0 INTERRUPT
TF0
(5 Bit) (8 Bit)
C /T 1
T 0 PIN
TR 0
Gate
INT 0 PIN
OSC ÷12
C /T 0 TL0 TH0 INTERRUPT
TF0
(8 Bit) (8 Bit)
C /T 1
T 0 PIN
TR 0
Gate
INT 0 PIN
OSC ÷12
C /T 0 TL0 TH0 INTERRUPT
TF0
(8 Bit) (8 Bit)
C /T 1
T 0 PIN
TR 0
Gate Reload
INT 0 PIN
TH0
(8 Bit)
OSC ÷12
C /T 0 TL0 INTERRUPT
TF0
(8 Bit)
C /T 1
T 0 PIN
TR 0
Gate
INT 0 PIN
TR1
TIMER 1
OSC ÷12
C /T 0
TL1 TH1 TF1
C /T 1
T 1PIN
INTERRUPT
TR1
Gate
INT 1 PIN
TIMER 1 – Mode 0
13 Bit Timer / Counter
OSC ÷12
C /T 0 TL1 TH1 INTERRUPT
TF1
(5 Bit) (8 Bit)
C /T 1
T 1PIN
TR1
Gate
INT 1 PIN
OSC ÷12
C /T 0 TL1 TH1 INTERRUPT
TF1
(8 Bit) (8 Bit)
C /T 1
T 1PIN
TR1
Gate
INT 1 PIN
OSC ÷12
C /T 0 TL1 TH1 INTERRUPT
TF1
(8 Bit) (8 Bit)
C /T 1
T 1PIN
TR1
Gate Reload
INT 1 PIN
TH1
(8 Bit)
• Example: Indicate which mode and which timer are selected for each
of the following.
(a) MOV TMOD, #01H (b) MOV TMOD, #20H (c) MOV TMOD, #12H
• Solution:
• Serial: To transfer to a device located many meters away, the serial method is used.
The data is sent one bit at a time.
• The start bit is always one bit, but the stop bit can be one or two
bits
• The start bit is always a 0 (low) and the stop bit(s) is 1 (high)
• As far as the conductor wire is concerned, the baud rate and bps are the
same.
1. SBUF Register
2. SCON Register
3. PCON Register
• We can set it to high by software and thereby double the baud rate.
• Timer 0 Overflow.
• Timer 1 Overflow.
• Reception/Transmission of Serial Character.
• External Event 0.
• External Event 1.
• Upon reset, all interrupts are disabled (masked), meaning that none
will be responded to by the microcontroller if they are activated.
--
• EA : Global enable/disable.
• --- : Reserved for additional interrupt hardware.
MOV IE,#08h
• ES : Enable Serial port interrupt.
or • ET1 : Enable Timer 1 control bit.
SETB ET1
• EX1 : Enable External 1 interrupt.
• ET0 : Enable Timer 0 control bit.
• EX0 : Enable External 0 interrupt.
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Enabling
• Example: Showand Disablingtoan
the instructions (a)Interrupt
enable the serial interrupt,
timer 0 interrupt, and external hardware interrupt 1 and (b) disable
(mask) the timer 0 interrupt, then (c) show how to disable all the
interrupts with a single instruction.
• Solution:
• (a) MOV IE,#10010110B ;enable serial, timer 0, EX1
• Another way to perform the same manipulation is:
• SETB IE.7 ;EA=1, global enable
• SETB IE.4 ;enable serial interrupt
• SETB IE.1 ;enable Timer 0 interrupt
• SETB IE.2 ;enable EX1
• (b) CLR IE.1 ;mask (disable) timer 0 interrupt only
• (c) CLR IE.7 ;disable all interrupts
Serial Port
INT 0 Pin
Timer 1 Pin