Chapter 8.

Pipelining
Dr. S Sathish Kumar
Professor, ISE Department,
RNSIT
Overview
 Pipelining is widely used in modern
processors.
 Pipelining improves system performance in
terms of throughput.
 Pipelined organization requires sophisticated
compilation techniques.
Basic Concepts
Making the Execution of
Programs Faster
 Use faster circuit technology to build the
processor and the main memory.
 Arrange the hardware so that more than one
operation can be performed at the same time.
 In the latter way, the number of operations
performed per second is increased even
though the elapsed time needed to perform
any one operation is not changed.
Traditional Pipeline Concept
 Laundry Example
 Ann, Brian, Cathy, Dave
each have one load of clothes A B C D
to wash, dry, and fold
 Washer takes 30 minutes

 Dryer takes 40 minutes

 “Folder” takes 20 minutes

Traditional Pipeline Concept

6 PM 7 8 9 10 11 Midnight

Time

30 40 20 30 40 20 30 40 20 30 40 20
 Sequential laundry takes 6 hours
A for 4 loads
 If they learned pipelining, how
long would laundry take?
B

D
Traditional Pipeline Concept

6 PM 7 8 9 10 11 Midnight

Time
T
a 30 40 40 40 40 20
s
k A
 Pipelined laundry takes
3.5 hours for 4 loads
O B
r
d C
e
r D
 Traditional Pipeline Concept
 Pipelining doesn’t help
latency of single task, it
6 PM 7 8 9 helps throughput of entire
workload
Time  Pipeline rate limited by
T slowest pipeline stage
a 30 40 40 40 40 20  Multiple tasks operating
s simultaneously using
A
k different resources
 Potential speedup = Number
O B pipe stages
r  Unbalanced lengths of pipe
d
stages reduces speedup
C
e
 Time to “fill” pipeline and
time to “drain” it reduces
r
D speedup
 Stall for Dependences
Use the Idea of Pipelining in a Computer

Fetch + Execution
T ime
I1 I2 I3
Time
Clock cycle 1 2 3 4
F E F E F E
1 1 2 2 3 3
Instruction

I1 F1 E1
(a) Sequential execution

I2 F2 E2
Interstage buffer
B1
I3 F3 E3

Instruction Ex ecution
fetch unit (c) Pipelined execution
unit

Figure 8.1. Basic idea of instruction pipelining.

(b) Hardware organization
Use the Idea of Pipelining in a Computer
Time
Clock cycle 1 2 3 4 5 6 7

Instruction

I1 F1 D1 E1 W1

Fetch + Decode I2 F2 D2 E2 W2
+ Execution + Write
I3 F3 D3 E3 W3

I4 F4 D4 E4 W4

(a) Instruction execution divided into four steps

Interstage buffers

D : Decode
F : Fetch instruction E: Execute W : Write
instruction and fetch operation results
operands
B1 B2 B3

(b) Hardware organization

Textbook page: 457

Figure 8.2. A 4-stage pipeline.

Role of Cache Memory
 Each pipeline stage is expected to complete in one
clock cycle.
 The clock period should be long enough to let the
slowest pipeline stage to complete.
 Faster stages can only wait for the slowest one to
complete.
 Since main memory is very slow compared to the
execution, if each instruction needs to be fetched
from main memory, pipeline is almost useless.
 Fortunately, we have cache.
Pipeline Performance
 The potential increase in performance
resulting from pipelining is proportional to the
number of pipeline stages.
 However, this increase would be achieved
only if all pipeline stages require the same
time to complete, and there is no interruption
throughout program execution.
 Unfortunately, this is not true.
 Pipeline Performance

Time
Clock cycle 1 2 3 4 5 6 7 8 9

Instruction
I1 F1 D1 E1 W1

I2 F2 D2 E2 W2

I3 F3 D3 E3 W3

I4 F4 D4 E4 W4

I5 F5 D5 E5

Figure 8.3. Effect of an execution operation taking more than one clock cycle.
Pipeline Performance
 The previous pipeline is said to have been stalled for two
clock cycles.
 Any condition that causes a pipeline to stall is called a
hazard.
 Data hazard – any condition in which either the source or
the destination operands of an instruction are not
available at the time expected in the pipeline. So some
operation has to be delayed, and the pipeline stalls.
 Instruction (control) hazard – a delay in the availability of
an instruction causes the pipeline to stall.
 Structural hazard – the situation when two instructions
require the use of a given hardware resource at the
same time.
 Pipeline Performance

Time
Clock cycle 1 2 3 4 5 6 7 8 9
Instruction Instruction
hazard I1 F1 D1 E1 W1

I2 F2 D2 E2 W2

I3 F3 D3 E3 W3

(a) Instruction execution steps in successive clock cycles

Time
Clock cycle 1 2 3 4 5 6 7 8 9

Stage
F: Fetch F1 F2 F2 F2 F2 F3
Idle periods –
D: Decode D1 idle idle idle D2 D3
stalls (bubbles)
E: Execute E1 idle idle idle E2 E3

W: Write W1 idle idle idle W2 W3

(b) Function performed by each processor stage in successive clock cycles

Figure 8.4. Pipeline stall caused by a cache miss in F2.

 Pipeline Performance
Load X(R1), R2

Time
Structural Clock cycle 1 2 3 4 5 6 7
hazard
Instruction
I1 F1 D1 E1 W1

I2 (Load) F2 D2 E2 M2 W2

I3 F3 D3 E3 W3

I4 F4 D4 E4

I5 F5 D5

Figure 8.5. Effect of a Load instruction on pipeline timing.

Pipeline Performance
 Again, pipelining does not result in individual
instructions being executed faster; rather, it is the
throughput that increases.
 Throughput is measured by the rate at which
instruction execution is completed.
 Pipeline stall causes degradation in pipeline
performance.
 We need to identify all hazards that may cause the
pipeline to stall and to find ways to minimize their
impact.
Quiz
 Four instructions, the I2 takes two clock
cycles for execution. Pls draw the figure for 4-
stage pipeline, and figure out the total cycles
needed for the four instructions to complete.
Data Hazards
Data Hazards
 We must ensure that the results obtained when instructions are
executed in a pipelined processor are identical to those obtained
when the same instructions are executed sequentially.
 Hazard occurs
A←3+A
B←4×A
 No hazard
A←5×C
B ← 20 + C
 When two operations depend on each other, they must be
executed sequentially in the correct order.
 Another example:
Mul R2, R3, R4
Add R5, R4, R6
Data Hazards
Time
Clock cycle 1 2 3 4 5 6 7 8 9

Instruction

I1 (Mul) F1 D1 E1 W1

I2 (Add) F2 D2 D2A E2 W2

I3 F3 D3 E3 W3

I4 F4 D4 E4 W4

Figure 8.6. Pipeline stalled by data dependency between D2 and W 1.

Figure 8.6. Pipeline stalled by data dependency between D 2 and W1.
Operand Forwarding
 Instead of from the register file, the second
instruction can get data directly from the
output of ALU after the previous instruction is
completed.
 A special arrangement needs to be made to
“forward” the output of ALU to the input of
ALU.
 Source 1
Source 2

SRC1 SRC2

Register
file

ALU

RSLT

Destination

(a) Datapath

SRC1,SRC2 RSLT

E: Execute W: Write
(ALU) (Register file)

Forwarding path

(b) P osition of the source and result registers in the processor pipeline

Figure 8.7. Operand forw arding in a pipelined processor.

Handling Data Hazards in
Software
 Let the compiler detect and handle the
hazard:
I1: Mul R2, R3, R4
NOP
NOP
I2: Add R5, R4, R6
 The compiler can reorder the instructions to
perform some useful work during the NOP
slots.
Side Effects
 The previous example is explicit and easily detected.
 Sometimes an instruction changes the contents of a register
other than the one named as the destination.
 When a location other than one explicitly named in an instruction
as a destination operand is affected, the instruction is said to
have a side effect. (Example?)
 Example: conditional code flags:
Add R1, R3
AddWithCarry R2, R4
 Instructions designed for execution on pipelined hardware should
have few side effects.
Instruction Hazards
Overview
 Whenever the stream of instructions supplied
by the instruction fetch unit is interrupted, the
pipeline stalls.
 Cache miss
 Branch
Unconditional Branches
Time
Clock cycle 1 2 3 4 5 6

Instruction
I1 F1 E1

I2 (Branch) F2 E2 Execution unit idle

I3 F3 X

Ik Fk Ek

Ik+1 Fk+1 Ek+1

Figure 8.8. An idle cycle caused by a branch instruction.

 Time
Clock cycle 1 2 3 4 5 6 7 8

Branch Timing I1 F1 D1 E1 W1

I2 (Branch) F2 D2 E2

I3 F3 D3 X

- Branch penalty I4 F4 X

Ik Fk Dk Ek Wk
- Reducing the penalty
Ik+1 Fk+1 Dk+1 E k+1

(a) Branch address computed in Execute stage

Time
Clock cycle 1 2 3 4 5 6 7

I1 F1 D1 E1 W1

I2 (Branch) F2 D2

I3 F3 X

Ik Fk Dk Ek Wk

Ik+1 Fk+1 D k+1 E k+1

(b) Branch address computed in Decode stage

Figure 8.9. Branch timing.

Instruction Queue and
Prefetching
Instruction fetch unit
Instruction queue
F : Fetch
instruction

D : Dispatch/
Decode E : Ex ecute W : Write
instruction results
unit

Figure 8.10. Use of an instruction queue in the hardware organization of Figure 8.2b.
Conditional Braches
 A conditional branch instruction introduces
the added hazard caused by the dependency
of the branch condition on the result of a
preceding instruction.
 The decision to branch cannot be made until
the execution of that instruction has been
completed.
 Branch instructions represent about 20% of
the dynamic instruction count of most
programs.
Delayed Branch
 The instructions in the delay slots are always
fetched. Therefore, we would like to arrange
for them to be fully executed whether or not
the branch is taken.
 The objective is to place useful instructions in
these slots.
 The effectiveness of the delayed branch
approach depends on how often it is possible
to reorder instructions.
Delayed Branch
LOOP Shift_left R1
Decrement R2
Branch=0 LOOP
NEXT Add R1,R3

(a) Original program loop

LOOP Decrement R2
Branch=0 LOOP
Shift_left R1
NEXT Add R1,R3

(b) Reordered instructions

Figure 8.12. Reordering of instructions for a delayed branch.

Delayed Branch
Time
Clock cycle 1 2 3 4 5 6 7 8

Instruction
Decrement F E

Branch F E

Shift (delay slot) F E

Decrement (Branch taken) F E

Branch F E

Shift (delay slot) F E

Add (Branch not taken) F E

Figure 8.13. Execution timing showing the delay slot being filled
during the last two passes through the loop in Figure 8.12.
Branch Prediction
 To predict whether or not a particular branch will be taken.
 Simplest form: assume branch will not take place and continue to
fetch instructions in sequential address order.
 Until the branch is evaluated, instruction execution along the
predicted path must be done on a speculative basis.
 Speculative execution: instructions are executed before the
processor is certain that they are in the correct execution
sequence.
 Need to be careful so that no processor registers or memory
locations are updated until it is confirmed that these instructions
should indeed be executed.
Incorrectly Predicted Branch
Time
Clock cycle 1 2 3 4 5 6

Instruction

I 1 (Compare) F1 D1 E1 W1

I 2 (Branch>0) F2 D 2 /P2 E2

I3 F3 D3 X

I4 F4 X

Ik Fk Dk

Figure 8.14. Timing when a branch decision has been incorrectly predicted
as not taken.
Branch Prediction
 Better performance can be achieved if we arrange
for some branch instructions to be predicted as
taken and others as not taken.
 Use hardware to observe whether the target
address is lower or higher than that of the branch
instruction.
 Let compiler include a branch prediction bit.
 So far the branch prediction decision is always the
same every time a given instruction is executed –
static branch prediction.
 Influence on
Instruction Sets
Overview
 Some instructions are much better suited to
pipeline execution than others.
 Addressing modes
 Conditional code flags
Addressing Modes
 Addressing modes include simple ones and
complex ones.
 In choosing the addressing modes to be
implemented in a pipelined processor, we
must consider the effect of each addressing
mode on instruction flow in the pipeline:
 Side effects
 The extent to which complex addressing modes cause
the pipeline to stall
 Whether a given mode is likely to be used by compilers
 Recall
Load X(R1), R2
Time
Clock cycle 1 2 3 4 5 6 7

Instruction

I1 F1 D1 E1 W1

I2 (Load) F2 D2 E2 M2 W2

I3 F3 D3 E3 W3

I4 F4 D4 E4

I5 F5 D5

Load (R1), R2 Figure 8.5. Effect of a Load instruction on pipeline timing.

Complex Addressing Mode
Load (X(R1)), R2

Time
Clock cycle 1 2 3 4 5 6 7

Load F D X + [R1] [X +[R1]] [[X +[R1]]] W

Forward

Next instruction F D E W

(a) Complex addressing mode

Simple Addressing Mode
Add #X, R1, R2
Load (R2), R2
Load (R2), R2

Add F D X + [R1] W

Load F D [X +[R1]] W

Load F D [[X +[R1]]] W

Next instruction F D E W

(b) Simple addressing mode

Addressing Modes
 In a pipelined processor, complex addressing
modes do not necessarily lead to faster execution.
 Advantage: reducing the number of instructions /
program space
 Disadvantage: cause pipeline to stall / more
hardware to decode / not convenient for compiler to
work with
 Conclusion: complex addressing modes are not
suitable for pipelined execution.
Addressing Modes
 Good addressing modes should have:
 Access to an operand does not require more than one
access to the memory
 Only load and store instruction access memory operands
 The addressing modes used do not have side effects
 Register, register indirect, index
Conditional Codes
 If an optimizing compiler attempts to reorder
instruction to avoid stalling the pipeline when
branches or data dependencies between
successive instructions occur, it must ensure
that reordering does not cause a change in
the outcome of a computation.
 The dependency introduced by the condition-
code flags reduces the flexibility available for
the compiler to reorder instructions.
Conditional Codes
Add R1,R2
Compare R3,R4
Branch=0 ...

(a) A program fragment

Compare R3,R4
Add R1,R2
Branch=0 ...

(b) Instructions reordered

Figure 8.17. Instruction reordering.
Conditional Codes
 Two conclusion:
 To provide flexibility in reordering instructions, the
condition-code flags should be affected by as few
instruction as possible.
 The compiler should be able to specify in which
instructions of a program the condition codes are
affected and in which they are not.
Datapath and Control
Considerations
 Bus A Bus B Bus C

Incrementer

Original Design PC

Register
file

Constant 4

MUX
A

ALU R

Instruction
decoder

IR

MDR

MAR

Memory bus Address

data lines lines

Figure 7.8. Three-b us organization of the datapath.

 Register
file

Pipelined Design

Bus A
A

Bus B
ALU R

- Separate instruction and data caches B

- PC is connected to IMAR

Bus C
- DMAR
- Separate MDR PC
- Buffers for ALU Control signal pipeline
- Instruction queue Incrementer
- Instruction decoder output
Instruction IMAR
decoder

Memory address
(Instruction fetches)
Instruction
queue

MDR/Write DMAR MDR/Read

Instruction cache

Memory address
- Reading an instruction from the instruction cache (Data access)

- Incrementing the PC
- Decoding an instruction
- Reading from or writing into the data cache Data cache
- Reading the contents of up to two regs
- Writing into one register in the reg file Figure 8.18. Datapath modified for pipelined execution, with
- Performing an ALU operation interstage buffers at the input and output of the ALU.
Superscalar Operation
Overview
 The maximum throughput of a pipelined processor
is one instruction per clock cycle.
 If we equip the processor with multiple processing
units to handle several instructions in parallel in
each processing stage, several instructions start
execution in the same clock cycle – multiple-issue.
 Processors are capable of achieving an instruction
execution throughput of more than one instruction
per cycle – superscalar processors.
 Multiple-issue requires a wider path to the cache
and multiple execution units.
Superscalar
F : Instruction
fetch unit

Instruction queue

Floating-
point
unit
Dispatch
unit W : Write
results

Integer
unit

Figure 8.19. A processor with two execution units.

Timing
Time
Clock cycle 1 2 3 4 5 6 7

I 1 (Fadd) F1 D1 E1A E 1B E 1C W1

I 2 (Add) F2 D2 E2 W2

I 3 (Fsub) F3 D3 E3 E3 E3 W3

I 4 (Sub) F4 D4 E4 W4

Figure 8.20. An example of instruction execution flow in the processor of Figure 8.19,
assuming no hazards are encountered.
Out-of-Order Execution
 Hazards
 Exceptions
 Imprecise exceptions
 Precise exceptions
Time
Clock cycle 1 2 3 4 5 6 7

I 1 (Fadd) F1 D1 E1A E 1B E 1C W1

I 2 (Add) F2 D2 E2 W2

I 3 (Fsub) F3 D3 E3A E 3B E 3C W3

I 4 (Sub) F4 D4 E4 W4

(a) Delayed write

Execution Completion
 It is desirable to used out-of-order execution, so that an
execution unit is freed to execute other instructions as soon as
possible.
 At the same time, instructions must be completed in program
order to allow precise exceptions.
 The use of temporary registers
 Commitment unit
Time
Clock cycle 1 2 3 4 5 6 7

I 1 (Fadd) F1 D1 E1A E 1B E 1C W1

I 2 (Add) F2 D2 E2 TW2 W2

I 3 (Fsub) F3 D3 E3A E 3B E 3C W3

I 4 (Sub) F4 D4 E4 TW4 W4

(b) Using temporary registers

 Performance
Considerations
Overview
 The execution time T of a program that has a
dynamic instruction count N is given by:
N S
T
R
where S is the average number of clock cycles it
takes to fetch and execute one instruction, and
R is the clock rate.
 Instruction throughput is defined as the number
of instructions executed per second.
R
Ps 
S
Overview
 An n-stage pipeline has the potential to increase the
throughput by n times.
 However, the only real measure of performance is
the total execution time of a program.
 Higher instruction throughput will not necessarily
lead to higher performance.
 Two questions regarding pipelining
 How much of this potential increase in instruction throughput can be
realized in practice?
 What is good value of n?
Number of Pipeline Stages
 Since an n-stage pipeline has the potential to
increase the throughput by n times, how about we
use a 10,000-stage pipeline?
 As the number of stages increase, the probability of
the pipeline being stalled increases.
 The inherent delay in the basic operations
increases.
 Hardware considerations (area, power, complexity,
…)