Introduction to Digital Logic

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Digital Circuits
 Combinatorial logic
 Results of an operation depend only on the
present inputs to the operation
 Uses: perform arithmetic, control data movement,
compare values for decision making
 Sequential logic
 Results depend on both the inputs to the operation
and the result of the previous operation
 Uses: counter

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COMBINATIONAL CIRCUITS
 AND A B C
 Result TRUE if and only if both 0 0 0
input operands are true 0 1 0
 C=A B 1 0 0
1 1 1
 OR
 Result TRUE if any input operands A B C
are true 0 0 0
 C=A+B 0 1 1
1 0 1
1 1 1
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COMBINATIONAL CIRCUITS
 NOT
A C
 Result TRUE if single input value is
0 1
FALSE
1 0
 C=A

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COMBINATIONAL CIRCUITS
 EXCLUSIVE-OR
A B C
 Result TRUE if either A or B is
0 0 0
TRUE but not both
0 1 1
 C=A⊕B
1 0 1
 Can be derived from
1 1 0
INCLUSIVE-OR, AND and NOT

A ⊕ B = (A + B)  ( A  B )
A xor B equals A or B but not both A and B

A ⊕ B = (A  B ) + ( B  A )
A xor B = either A and not B or B and not A

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Boolean Algebra Operations
 Valid for INCLUSIVE-OR, AND, XOR
 Associative
 A + ( B + C ) = ( A + B ) + C
 Distributive

A  ( B + C ) = A  B +A  C
 Commutative

A + B = B + A
 DeMorgan’s Theorems
 A + B = A  B

A  B = A + B

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Computer Implementation
 Gates or logical gates
 Integrated circuits constructed from transistor
switches and other electronic components
 VLSI: very large-scale integration

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Boolean Algebra
Implementation
 Single type of gate appropriately combined
 2 possibilities
 NAND gate: AND operation followed by a NOT operation
 NOR gate: INCLUSIVE-OR followed by a NOT operation

Note:  indicates a NOT operation

 Flip-flop: basic memory

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Flip-Flop Types with State Tables

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Multiplexer
Multiplexer: A multiplexer is a combinational circuit that has 2 n input lines and a
single output line. Simply, the multiplexer is a multi-input and single-output
combinational circuit. The binary information is received from the input lines and
directed to the output line. Based on the values of the selection lines, one of these
data inputs will be connected to the output.
There are n selection lines and 2n input lines. So, there is a total of 2N possible
combinations of inputs. A multiplexer is also treated as Mux.

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2:1 Multiplexer
For Example, 2:1 Multiplexer
A simple 2:1 Mux will have 2 input lines I0 & I1 and one select line x and a single
output F. The select line can take a value either 0 or 1. If x takes a value 0, the
input I0 is selected and the output Y = I0

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4:1 Multiplexer

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Basic Gates Using Multiplexer
 Implementation of Not Gate Using Multiplexer

 Implementation of OR Gate Using Multiplexer

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Basic Gates Using Multiplexer
 Implementation of AND Gate Using 2:1 Multiplexer

 Implementation of Nand Gate Using 2:1 Multiplexer

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D-flipflop

In the D flip-flops, the output can only be changed at the clock edge, and if the
input changes at other times, the output will be unaffected.

The change of state of the output is dependent on the rising edge of the clock.
The output (Q) is the same as the input and can only change at the rising edge of
the clock.

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WHY WE USE D-FLIPFLOP IN VLSI DESIGN

 As Data Need to be Propagated from one Point to another point without

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Simplicity
D-flipflops have a straightforward design with a single data input. This
simplicity makes them easy to implement and understand.
 Single data-input
D-flipflops have a single input(D),Simplifying the logic and makes it easier
to comprehend and reduces the chances of errors.
 Truth-table:
It states that the Q output follow the D-input when the clock edge occurs.
 Binary Storage:
Stores single bit of information, representing a binary state(0 or 1).
 Clear Input and Output Timing:
Input is Sampled at the clock edge and the output is updated accordingly.

They serve as a fundamental building block in digital design.

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Edge-Triggered operation
 D-flipflops are Edge triggered, Meaning they change the state on clock
edge, This Allows for better synchronization in digital systems Which is
crucial for avoiding timing issues.

 Edge Triggered Flipflops have an Improved timing Behavior as

 Edge Triggered Flipflop Responds only on the transition on the Clock

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Use in Sequential Circuits
 D-flipflops are often used in sequential circuits like register and memory
elements due to their ability to store a single bit of information.

 Their clear separation of input and output timing helps maintain proper
sequencing in such circuits.

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Reduced Clock-to-Q-delay
 D-flipflops generally have a Short Clock-to-q-delay compared to other
types of flip flops making them suitable for the applications where fast
clocking is required.
 Clock-to-Q-delay is the time take by the flipflops output to respond to a
clock signal
A reduced delay means faster response time which is essential for meeting
timing Requirements.
 Enhanced Signal Integrity-faster Clock-to-q-delay contributes to better
signal integrity, As Maintaining signal integrity is critical to prevent setup
and hold timing issues.
 Low power consumptions: As it spends less time to activate the states
due to less clock-to-q-delay.
 Higher performance can be achieved.

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Why Not other Flipflops
 D-Flipflops Has a simpler structure when compared to SR,JK,T flipflops
 We may see some possibilities of invalid and forbidden states in other
flipflop which can be avoided in D-flipflop
 D-flipflop has a single input which simplifies the control logic
 We wont Use T flipflop as they toggle their output on each clock edge
when T input is high. Due to this timing becomes complex and
managing timing constraints becomes critical.As toggling is not the
primary requirement in VLSI Design so we won't use T flipflops.
 In SR flipflops when both inputs are set to 1, they enter to forbidden
state leading to unpredictable behaviour. Complex in nature, sensitive
to Noise, Power Consumption is more. Direct need of set and reset
options is not prevalent(most common)
 In JK flipflops are more Complex, toggling behaviour of jk flipflops
introduces race conditions, this may lead to complexity in timing. They
require additional logic to handle specific conditions and ensure proper
operations, Power consumption will be more due to this additional logic.
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Thank You

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