Digital Integrated

Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic

The Inverter
July 30, 2002

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 The CMOS Inverter: A First Glance
V DD

V in V out

CL

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 Two Inverters
Share power and ground

Abut cells

VDD

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 CMOS Inverter
First-Order DC Analysis
V DD V DD

Rp
VOL = 0
VOH = VDD
V out VM = f(Rn, Rp)
V out

Rn

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 CMOS Inverter: Transient Response
V DD V DD

Rp tpHL = f(Ron.CL)
= 0.69 RonCL

V out
V out
CL CL
Rn

v out(t) = (1 - e-t/) V
V in 5 0 V in 5 V DD
t = ln(2)t = 0.69
(a) Low-to-high (b) High-to-low

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 Voltage Transfer
Characteristic

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CMOS Inverter VTC
Vout NMOS off
2.5 PMOS res
NMOS s at
PMOS res
2

NMOS sat
1.5

PMOS sat
1

NMOS res
PMOS sat NMOS res
0.5

PMOS off

0.5 1 1.5 2 2 .5 Vin

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 Switching Threshold as a function of
Transistor Ratio
Assuming velocity saturated device
1.8
At VM, VGS=VDS, IN=IP
1.7

1.6

1.5

1.4
V (V)

1.3
M

1.2

1.1

0.9

0.8
0 1
10 10
W /W
p n
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 Determining VIH and VIL
Vout

V OH

VM

V in
V OL
V IL V IH

A simplified approach

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 Inverter Gain
0
Differentiate current
-2 equation at Vin=VM and
-4 some simplifications
-6

-8
gain

-10

-12

-14

-16

-18
0 0.5 1 1.5 2 2.5 G dependent mainly on
Vin (V) technological
parameters
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 Robustness Issues : Impact of Process
Variations
2.5

2
Good PMOS
Bad NMOS
1.5
Vout(V)

Nominal

1
Good NMOS
Bad PMOS

0.5

0
0 0.5 1 1.5 2 2.5
Vin (V)

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 Propagation Delay

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 CMOS Inverter Propagation Delay
VDD

tpHL = f(Ron.CL)
= 0.69 RonCL

Vout
Vout ln(0.5)
CL
1 VDD
Ron

0.5
0.36

Vin = V DD
t
RonCL

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 Transient Response

2.5
3
?
2

1.5
Vout(V)

tpLH tpHL
1

0.5

-0.5
0 0.5 1 1.5 2 2.5
t (sec) -10
x 10

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 Design for Performance
 Keep capacitances small
 Increase transistor sizes
 watch out for self-loading!
 Increase VDD  decrease RON

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 Device Sizing
-11
x 10
3.8

3.6 (for fixed load)

3.4

3.2
tp(sec)

2.8 Self-loading effect:

2.6 Intrinsic capacitances
dominate
2.4

2.2

2
2 4 6 8 10 12 14
S

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 NMOS/PMOS ratio
-11
x 10
5

tpLH tpHL
4.5

tp  = Wp/Wn
tp(sec)

3.5

3
1 1.5 2 2.5 3 3.5 4 4.5 5


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 Progressive Sizing : Inverter Chain

In Out

CL

If CL is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?

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 Inverter Delay
• Minimum length devices, L=0.25m
• Assume that for WP = 2WN =2W 2W
• same pull-up and pull-down currents
• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays W
• Analyze as an RC network
1 1
 WP   WN 
RP  Runit    Runit    RN  RW
 Wunit   Wunit 
Delay (D): tpHL = (ln 2) RNCL tpLH = (ln 2) RPCL
W
Load for the driver: C gin 3 Cunit
Wunit
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 Delay Formula
Cint = Cgin with   1
f = CL/Cgin - effective fanout
RW = Runit/W ; Cint =WCunit

t p  RW Cint 1  C L / Cint   t p 0 1  f /  

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 Apply to Inverter Chain
In Out

1 2 N CL

tp = tp1 + tp2 + …+ tpN

 C gin , j 1 
t pj ~ tp 01  
 C 
 gin , j 
N N  C gin, j 1 
t p   t p , j  t p 0  1  , C gin, N 1  C L
 C
i 1 

j 1 gin , j 

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 Optimal Tapering for Given N
Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N

Minimize the delay, find N - 1 partial derivatives

Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1

Size of each stage is the geometric mean of two neighbors

C gin , j  C gin , j 1C gin , j 1

- each stage has the same effective fanout (Cout/Cin)

- each stage has the same delay

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 Optimum Delay and Number of
Stages
When each stage is sized by f and has same eff. fanout f:
f N
 F  C L / C gin,1

Effective fanout of each stage:

f NF
Minimum path delay


t p  Nt p 0 1  N F /  
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 Example

In Out

1 f f2 CL= 8 C1
C1

CL/C1 has to be evenly distributed across N = 3 stages:

f 38 2

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 Optimum Number of Stages
For a given load, CL and given input capacitance Cin
Find optimal sizing f
ln F
C L  F  Cin  f Cin with N 
N

ln f
t p 0 ln F  f  
t p  Nt p 0 F /   1 
1/ N
  
  ln f ln f 
t p t p 0 ln F ln f  1   f
  0
f  ln f 2

For  = 0, f = e, N = lnF f  exp1   f 

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 Optimum Effective Fanout f
Optimum f for given process defined by 
f  exp1   f 
fopt = 3.6
for =1

(numerical solution)

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 Buffer Design
N f tp
1 64 1 64 65

1 8 64 2 8 18

1 4 16 64 3 4 15

1 64 4 2.8 15.3
2.8 8 22.6

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 Power Dissipation

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Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors

• Short Circuit Currents

Short Circuit Path between Supply Rails during Switching

• Leakage
Leaking diodes and transistors

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 Dynamic Power Dissipation
Vdd

Vin Vout

CL

Energy/transition = CL * Vdd2

Power = Energy/transition * f = CL * Vdd2 * f

Not a function of transistor sizes if internal loading ignored!

Need to reduce CL, Vdd, and f to reduce power.

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 Node Transition Activity and Power
Consider switching a CMOS gate for N clock cycles

E = C  V 2  n N 
N L dd
EN : the energy consumed for N clock cycles
n(N): the number of 0->1 transition in N clock cycles

EN 2
n N 
P avg = lim --------  fclk =  lim ------------  C  Vdd  f clk
N N N   N  L

n N 
0  1 = lim ------------
N N

=  V 2 f
0  1  L  dd  clk
P C
avg

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 Transistor Sizing for Minimum Energy
In Out

Cext
Cg1 1 f

 Goal: Minimize Energy of whole circuit

 Design parameters: f and VDD
 tp  tpref of circuit with f=1 and VDD =Vref

VDD
t p0 
VDD  VTE

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 Transistor Sizing (2)
 Energy for single Transition

E  VDD
2
C g1 1   1  f   F 
2
E  VDD   2  2 f  F  For reference
   
 
Eref  Vref   4  F  circuit f=1

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 Transistor Sizing (3)
E/Eref=f(f)

1.5

F=1

2
normalized energy

0.5
10

20

0
2 3 4 5 6 7 1 2 3 4 5 6 7
f f

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 Short Circuit Currents
Vdd

Vin Vout

CL

0.15

0.10
IVDD (mA)

0.05

0.0 1.0 2.0 3.0 4.0 5.0

Vin (V)

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 Minimizing Short-Circuit Power

Keep output rise/fall times larger than input rise/fall times

Then it shorts the subsequent stages!!

Match input and output rise/fall times !!!

 caters for increased loads also.

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 Leakage
Vdd

Vout

Drain Junction
Leakage

Sub-Threshold
Current

Sub-threshold current one of most compelling issues

Sub-Threshold
in low-energy circuitCurrent
design!Dominant Factor

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 Reverse-Biased Diode Leakage
GATE

p+ p+
N

Reverse Leakage Current

+
V
- dd

IDL = JS  A

2
JS = JS
1-5pA/ mpA/m2
= 10-100 for a 1.2 m
at 25 degCMOS technology
C for 0.25m CMOS
JS doubles for every 9 deg C!
Js double with every 9oC increase in temperature

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 Subthreshold Leakage Component

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 Static Power Consumption
Vdd

Istat
Vout

CL
Vin = 5V

Pstat = P(In=1).Vdd . Istat

Wasted•energy … over dynamic consumption

Dominates
Should be avoided in almost all cases,
• Not a function of switching frequency
but could help reducing energy in others (e.g. sense amps)

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 Principles for Power Reduction
 Prime choice: Reduce voltage!
 Recent years have seen an acceleration in
supply voltage reduction
 Design at very low voltages still open question
(0.6 … 0.9 V by 2010!)
 Reduce switching activity
 Reduce physical capacitance
 Device Sizing: for F=20
– fopt(energy)=3.53, fopt(performance)=4.47

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 Total Power

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 Power-Delay Product, Energy per operation,
Energy-Delay Product

Above is confusing as performance is missing

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