ADC DESIGN

Engr. Rana Muhammad Shahid Jamil

Problem
• Real World Signals are Analog in nature
• Voltage, Current etc
• We want to do complex processing on these signals to get information
or make decisions
• Sensor Monitor and Control Systems
• Mobile Communication
• Convolution/Filtering
• Fourier Transform
Solution 1
• Use analog components for signal processing
• Advantages
• Very High Speeds
• Power Efficient
• Disadvantages
• Tolerances/Accuracy
• Specialized for a specific task
• Different hardware for different function
Solution 2
• Use a microprocessor/microcontroller/FPGA for signal processing
• Advantages
• Reconfigurable/Programmable
• General Purpose
• High Accuracies
• Ease of implementation
• Disadvantages
• Limited speeds
Remarks
• Due to its ease of implementation and reconfigurability, 2nd Solution is
preferred.
• But it can only process digital signals.
• So we need a device that can accurately convert analog signals to
digital i-e We need an ADC
Analog to Digital Converter (ADC)
• Converts analog electrical signals to digital signals
• These digital signals can be processed microcontrollers/FPGAs
• Many types of ADCs
• Flash ADCs
• SAR ADCs
• ADCs
ADC Basics
• Vref is maximum input range of
ADC
• Minimum voltage change that
changes code is dictated by Vref
and ADC resolution
Chip 1
P1: 1GHz FM Radio Receiver

1001 - 1008 MHz

Oman-1:
Band pass
Filter LNA Mixer
Band Pass
IF Filter
Variable Gain
Amplifier FM Demod ulator
Audio Amp Audio 65nm CMOS Chip-1
Gain=20- Baseband
BW=8 MH z BW=1 MH z signal 0-20
Passband: 1001-1008 MHz
30 dB
IF=10 MHz KHz P4: Digital Baseband Processor

Quartz Low Pass Filter Audio

Crystal 8-bit DAC Speaker
Amp
++--
Phase Charge A/D 4-bit A/D 4-bit Digital Demodulator
Mux D/A 16 DAC
Detector Pump MSB LSB
Filtering / Equalization

Voltage
Integer N Controlled Non-Overlapping Clock Input/Output
Divider Oscillator

N 991 - 998 MH z or
CLK
1011-1018 MHz
N
AN
Trained
P2: Multichannel Phase Locked Loop P3: 25MSPS, 8-bit Two Stage ADC

P5: AI based Voice unTrained

Recognition
Let’s make sense of this………….
Transmitter Module
FM Tx 1
101 MHz

FM Tx 2
102 MHz

101-108 1001-1008
MHz MHz

LNA Amp

Gain: 25-35 BPF:

dB Passband: 1001-
900 1008 MHz
FM Tx 8 MHz
108 MHz
Up Conversion Module

FM Transmission Module
Chip 1
P1: 1GHz FM Radio Receiver

1001 - 1008 MHz

Oman-1:
Band pass
Filter LNA Mixer
Band Pass
IF Filter
Variable Gain
Amplifier FM Demod ulator
Audio Amp Audio 65nm CMOS Chip-1
Gain=20- Baseband
BW=8 MH z BW=1 MH z signal 0-20
Passband: 1001-1008 MHz
30 dB
IF=10 MHz KHz P4: Digital Baseband Processor

Quartz Low Pass Filter Audio

Crystal 8-bit DAC Speaker
Amp
++--
Phase Charge A/D 4-bit A/D 4-bit Digital Demodulator
Mux D/A 16 DAC
Detector Pump MSB LSB
Filtering / Equalization

Voltage
Integer N Controlled Non-Overlapping Clock Input/Output
Divider Oscillator

N 991 - 998 MH z or
CLK
1011-1018 MHz
N
AN
Trained
P2: Multichannel Phase Locked Loop P3: 25MSPS, 8-bit Two Stage ADC

P5: AI based Voice unTrained

Recognition
How It Goes………
• Up Converted FM Modulated Signal is at center frequency 920MHz
• The mixer down-converts the required channel to intermediate
frequency of 10MHz
• The channels are at a spacing of 1MHz.
• The maximum frequency is 10.1MHz
• The minimum sampling rate should be 20.2MHz (Why??).
• Which architecture should be used ???
Specifications
Specification Value
Sampling Rate 25 MSPS
Resolution 8-bits
Architecture Flash 2-Stage
VDD 1V
Technology TSMC 65nm Bulk CMOS
Temperature 0-70 oC (Commercial)

• Many Other very important Performance Parameters like SNR, Offset, Power, INL/DNL etc.
• But for the sake of simplicity we will ignore them here.
• We will see them during design
Proposed ADC Architecture

++--
A/D 4-bit A/D 4-bit
Mux D/A 16
MSB LSB

Non-Overlapping Clock

CLK
Let’s get down to technicalities…….!
• Target Schematic design will be at 33MSPS!!!......WHY??
• Layout Parasitic delays will inevitably slow down the circuit.
• Design margin of speed in schematic will help us compensate that
delay without doing too many layout iterations.
Timing Constraints
15ns
• Fclk=33MSPS => Tclk=30ns (50% Duty Cycle)
• Tracking/Sampling Time= 30/2 =15ns
• Hold/Conversion Time=15ns
• Our conversion must complete within 15ns at all
process corners and temperature range
15ns
Timing Distribution
15 ns 4 ns 4 ns 3 ns 4 ns

++--
A/D 4-bit A/D 4-bit
Sample/ D/A 16
Hold MSB LSB

Non-Overlapping Clock

*If two phases are

required
CLK
Circuit Implementations
Sample Hold
• A simple transmission Gate CLK

Switch
• A capacitor to hold charge IN OUT

• A buffer to drive resistor

string
Resistor String Flash ADC
VIN
VREF

• Very Simple
MSB

• Requires Comparators
• Guaranteed Monotonicity
• Encoder required

Thermometer
code
• Conversion time <= 4ns

LSB
Resistor String DAC
VREF

• Very Simple
• Uses thermometer Code
• Guaranteed Monotonicity
• Compatible with our ADC
• Conversion time <= 4ns
Vout
Subtractor and Multiplication
R
• Opamp based subtraction
• Opamp based multiplication R Vout
V2
V1 V1-V2
• All resistors are equal R
• All resistors must match in layout R

• Result valid within 3ns

Thermometer to Binary Encoder
• Both ADCs produce 4-bit
thermometer code
• An encoder must be used to
convert this thermometer code
to binary code
• Propagation delay <=1ns
Task Distribution
• Sample-Hold Circuit
• 4-bit ADC
• 4-bit DAC
• Subtraction and Multiplication
• Encoder, Clock Divider and Input Mux
A NOTE ON LAYOUT
• High speed circuits are very sensitive to parasitics.
• Symmetry must be ensured to minimize offsets.
• Resistors’ layout matching in ADC/DAC and opamp feedback is
extremely important.
• Good layout techniques (Interdigitation, common centroid,
symmetry, noise decoupling etc) must be followed.
• Layout planning should be in the mind of designer even at the
schematic level.