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Addressing Modes of 8086

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Addressing Modes of 8086

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RX Gamer
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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ADDRESSING MODES OF

8086
SANDEEP KHANTWAL
ASSISTANT PROFESSOR (ECE)
Addressing modes of 8086:

 Addressing mode indicates a way of locating


data or operands.
 The addressing modes describe the types of

operands and the way they are accessed for


executing an instruction.
 According to the flow of instruction

execution, the instructions may be


categorized as
◦ Sequential control flow instructions and
◦ Control transfer instructions
Addressing modes of 8086
 Sequential control flow instructions are the instructions,
which after execution, transfer control to the next
instruction appearing immediately after it (in the
sequence) in the program. For example, the arithmetic,
logic, data transfer and processor control instructions
are sequential control flow instructions.

The control transfer instructions, on the other hand,


transfer control to some predefined address or the
address somehow specified in the instruction, after
their execution. For example, INT, CALL, RET and JUMP
instructions fall under this category.
The addressing modes for sequential control transfer
instructions are:

 Immediate: In this type of addressing, immediate data is a part of


instruction and appears in the form of successive byte or bytes.
 Ex: MOV AX, 0005H

 In the above example, 0005H is the immediate data. The


immediate data may be 8-bit or 16-bit in size.
 Direct: In the direct addressing mode a 16-bit memory address
(offset) is directly specified in the instruction as a part of it.

 Ex: MOV AX, [5000H]


 Here, data resides in a memory location in the data segment,
whose effective address may be completed using 5000H as the
offset address and content of DS as segment address. The
effective address here, is 10H * DS + 5000H.
Addressing modes of 8086
 Register: In register addressing mode, the data is stored in a register
and is referred using the particular register. All the registers, except IP,
may be used in this mode.
 Ex: MOV BX, AX
 Register Indirect: Sometimes, the address of the memory location, which
contains data or operand, is determined in an indirect way, using the
offset register. This mode of addressing is known as register indirect
mode. In this addressing mode, the offset address of data is in either BX
or SI or DI register. The default segment is either DS or ES. The data is
supposed to be available at the address pointed to by the content of any
of the above registers in the default data segment.

 Ex: MOV AX, [BX]
 Here, data is present in a memory location in DS whose offset address is
in BX. The effective address of the data is given as 10H * DS+[BX].
Addressing modes of 8086
 Indexed: In this addressing mode, offset of the operand is stored
in one of the index registers. DS and ES are the default segments
for index registers, SI and DI respectively. This is a special case
of register indirect addressing mode.

 Ex: MOV AX, [SI]


 Here, data is available at an offset address stored in SI in DS. The
effective address, in this case, is computed as 10*DS+[SI].
 Register Relative: In this addressing mode, the data is available
at an effective address formed by adding an 8-bit or 16-bit
displacement with the content of any one of the registers BX, BP,
SI and DI in the default (either DS or ES) segment.
 Ex: MOV AX, 50H[BX]

 Here, the effective address is given as 10H *DS+50H+[BX]


Addressing modes of 8086
 Based Indexed: The effective address of data is formed, in this addressing mode,
by adding content of a base register (any one of BX or BP) to the content of an
index register (any one of SI or DI). The default segment register may be ES or DS.
 Ex: MOV AX, [BX][SI]

 Here, BX is the base register and SI is the index register the effective address is
computed as 10H * DS + [BX] + [SI].

Relative Based Indexed: The effective address is formed by adding an 8 or 16-bit


displacement with the sum of the contents of any one of the base register (BX or
BP) and any one of the index register, in a default segment.

 Ex: MOV AX, 50H [BX] [SI]
 Here, 50H is an immediate displacement, BX is base register and SI is an index
register the effective address of data is computed as
 10H * DS + [BX] + [SI] + 50H
PIN DIAGRAM OF 8086
PIN DESCRIPTION OF 8086
 READY: This is the acknowledgement from the slow devices or memory that
they have completed the data transfer operation. This signal is active high.

 INTR: Interrupt Request: Interrupt request is used to request a hardware
interrupt of INTR is held high when interrupt enable flag is set, the 8086
enters an interrupt acknowledgement cycle after the current instruction has
completed its execution.

 TEST : This input is tested by “WAIT” instruction. If the TEST input goes low;
execution will continue. Else the
 processor remains in an idle state.

 NMI- Non-maskable Interrupt: The non-maskable interrupt input is similar
to INTR except that the NMI interrupt does not check for interrupt enable
flag is at logic 1, i.e, NMI is not maskable internally by software. If NMI is
activated, the interrupt input uses interrupt vector 2.
PIN DESCRIPTION OF 8086
 RESET: The reset input causes the microprocessor to reset itself. When
8086 reset, it restarts the execution from memory location FFFF0H.
The reset signal is active high and must be active for at least four clock
cycles.
 CLK: Clock input: The clock input signal provides the basic timing
input signal for processor and bus control operation.
 It is asymmetric square wave with 33% duty cycle.

 VCC (+5V): Power supply for the operation of the internal circuit
 GND: Ground for the internal circuit

 MN / MX : The minimum/maximum mode signal to select the mode of


operation either in minimum or maximum
 mode configuration. Logic 1 indicates minimum mode.

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