Computer System and

Programming
Dr. Abdullah Waqas
 Introduction
• Binary numbers
• All computers work with 0’s and 1’s so it is like learning alphabets before
learning English
• Base conversion
• For convenience, people use other bases (like decimal, hexdecimal) and we need
to know how to convert from one to another.
• Number systems
• There are more than one way to express a number in binary. So 1010 could be -
2, -5 or -6 and need to know which one.
• A/D and D/A conversion
• Real world signals come in continuous/analog format and it is good to know
generally how they become 0’s and 1’s (and visa versa).
Digital
• Digital = discrete
Decimal BCD
• Binary codes (example: BCD)
Symbols Code
• Decimal digits 0-9
0 0000
1 0001
• Binary codes 2 0010
• Represent symbols using binary digits 3 0011
(bits)
4 0100
• Digital computers: 5 0101
• I/O is digital 6 0110
• ASCII, decimal, etc. 7 0111
• Internal representation is binary 8 1000
• Process information in bits 9 1001
The basics: Binary numbers

• Bases we will use

• Binary: Base 2
• Octal: Base 8
• Decimal: Base 10
• Hexadecimal: Base 16

• Positional number system

• 1012= 1×22 + 0×21 + 1×20
• 638 = 6×81 + 3×80
• A116= 10×161 + 1×160

• Addition and subtraction

1011 1011
+ 1010 – 0110
10101 0101
Binary → hex/decimal/octal conversion

• Conversion from binary to octal/hex

• Binary: 10011110001
• Octal: 10 | 011 | 110 | 001=23618
• Hex: 100 | 1111 | 0001=4F116

• Conversion from binary to decimal

• 1012= 1×22 + 0×21 + 1×20 = 510
• 63.48 = 6×81 + 3×80 + 4×8–1 = 51.510
• A116= 10×161 + 1×160 = 16110
Decimal→ binary/octal/hex conversion

• Why does this work?

• N=5610=1110002
• Q=N/2=56/2=111000/2=11100 remainder 0

• Each successive divide liberates an LSB (least significant bit)

• End of Lecture 1
Number systems

• How do we write negative binary numbers?

• Historically: 3 approaches
• Sign-and-magnitude
• Ones-complement
• Twos-complement

• For all 3, the most-significant bit (MSB) is the sign digit

• 0 ≡ positive
• 1 ≡ negative

• twos-complement is the important one

• Simplifies arithmetic
• Used almost universally
Sign-and-magnitude
• The most-significant bit (MSB) is the sign digit
• 0 ≡ positive
• 1 ≡ negative

• The remaining bits are the number’s magnitude

• Problem 1: Two representations for zero

• 0 = 0000 and also –0 = 1000

• Problem 2: Arithmetic is cumbersome

Ones-complement
• Negative number: Bitwise complement positive number
• 0011 ≡ 310
• 1100 ≡ –310

• Solves the arithmetic problem

• Remaining problem: Two representations for zero

• 0 = 0000 and also –0 = 1111
Twos-complement
• Negative number: Bitwise complement plus one
• 0011 ≡ 310
• 1101 ≡ –310
–1 0
• Number wheel
–2 1111 0000 +1

–3 1110 0001 +2
 Only one zero! 1101 0010
–4 +3
1100 0011
 MSB is the sign digit
 0 ≡ positive – 5 1011 0100 + 4
1010 0101
 1 ≡ negative
–6 1001 0110 +5

–7 1000 0111 +6
–8 +7
Twos-complement (con’t)
• Complementing a complement  the original number

• Arithmetic is easy
• Subtraction = negation and addition
• Easy to implement in hardware
Miscellaneous

• Twos-complement of non-integers
• 1.687510 = 01.10112
• –1.687510 = 10.01012

• Sign extension
• Write +6 and –6 as twos complement
• 0110 and 1010
• Sign extend to 8-bit bytes
• 00000110 and 11111010

• Can’t infer a representation from a number

• 11001 is 25 (unsigned)
• 11001 is –9 (sign magnitude)
• 11001 is –6 (ones complement)
• 11001 is –7 (twos complement)
Twos-complement overflow
• Summing two positive numbers gives a negative result

• Summing two negative numbers gives a positive result

–1 0 –1 0
–2 1111 0000 + 1 –2 1111 0000 + 1
–3 1110 0001 + 2 –3 1110 0001 + 2
1101 0010 1101 0010
– 4 1100 0011 + 3 – 4 1100 0011 + 3
– 5 1011 0100 + 4 – 5 1011 0100 + 4
1010 0101 1010 0101
• Make sure to have enough bits to handle overflow
–6 1001 0110 + 5 –6 1001 0110 + 5
–7 1000 0111 + 6 –7 1000 0111 + 6
–8 +7 –8 +7

6 + 4 ⇒ –6 –7 – 3 ⇒ +6
Gray and BCD codes

Decimal Gray Decimal BCD

Symbols Code Symbols Code
0 0000 0 0000
1 0001 1 0001
2 0011 2 0010
3 0010 3 0011
4 0110 4 0100
5 0111 5 0101
6 0101 6 0110
7 0100 7 0111
8 1100 8 1000
9 1101 9 1001
The physical world is analog

• Digital systems need to

• Measure analog quantities
• Speech waveforms, etc
• Control analog systems
• Drive motors, etc

• How do we connect the analog and digital domains?

• Analog-to-digital converter (A/D)
• Example: CD recording
• Digital-to-analog converter (D/A)
• Example: CD playback
Sampling
• Quantization
• Conversion from analog to
discrete values

• Quantizing a signal
• We sample it

Datel Data Acquisition and

Conversion Handbook
Conversion
• Encoding
• Assigning a digital word to each
discrete value

• Encoding a quantized signal

• Encode the samples
• Typically Gray or binary codes

Datel Data Acquisition and

Conversion Handbook
Computer Organization
3 Fundamental Components of Computer

• The CPU (ALU, Control Unit, Registers)

• The Memory Subsystem (Stored Data)
• The I/O subsystem (I/O devices)

Address Bus
Data Bus Memory
CPU
Control Bus Subsystem

I/O Device
Subsystem 20
Each of these Components are connected
through Buses.
• BUS - Physically a set of wires. The components of the Computer are
connected to these buses.
• Address Bus
• Data Bus
• Control Bus

21
Address Bus

• Used to specify the address of the memory location to access.

• Each I/O devices has a unique address. (monitor, mouse, cd-rom)
• CPU reads data or instructions from other locations by specifying the
address of its location.
• CPU always outputs to the address bus and never reads from it.

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Data Bus

• Actual data is transferred via the data bus.

• When the cpu sends an address to memory, the memory will send
data via the data bus in return to the cpu.

23
Control Bus

• Collection of individual control signals.

• Whether the cpu will read or write data.
• CPU is accessing memory or an I/O device
• Memory or I/O is ready to transfer data

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I/O Bus or Local Bus

• In today’s computers the the I/O controller will have an extra bus
called the I/O bus.
• The I/O bus will be used to access all other I/O devices connected to
the system.
• Example: PCI bus

25
Instruction Cycles

• Procedure the CPU goes through to process an instruction.

• 1. Fetch - get instruction
• 2. Decode - interperate the instruction
• 3. Execute - run the instruction.

26
CPU organization

• CPU controls the Computer

• The CPU will fetch, decode and execute instructions.
• The CPU has three internal sections: register section, ALU and
Control Unit

27
Register Section

• Includes collection of registers and a bus.

• Processor’s instruction set architecture are found in this section.
• Non accessible registers by the programmer. These are to be used
for registers to latch the address being accessed and a temp storage
register.

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Arithmetic/Logic Unit (ALU)

• Performs most Arithmetic and logical operations.

• Retrieves and stores its information with the register section of the
CPU.

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MEMORY ORGANIZATION

• Memory Hierarchy

• Main Memory

• Auxiliary Memory

• Associative Memory

• Cache Memory

• Virtual Memory

• Memory Management Hardware`

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Memory
Main memory consists of a number of
storage locations, each of which is
identified by a unique address
The ability of the CPU to identify each
location is known as its addressability

Each location stores a word i.e. the

number of bits that can be processed by
the CPU in a single operation. Word
length may be typically 16, 24, 32 or as
many as 64 bits.

A large word length improves system

performance, though may be less efficient on
occasions when the full word length is not
used

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 Memory Hierarchy

MEMORY HIERARCHY

Memory Hierarchy is to obtain the highest possible

access speed while minimizing the total cost of the memory system
Auxiliary memory
Magnetic
tapes I/O Main
processor memory
Magnetic
disks

CPU Cache
memory

Register

Cache

Main Memory

Magnetic Disk

Magnetic Tape
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Memory Subsystem

• 2 Types of Memory:
• ROM : Read Only Memory
• Program that is loaded into memory and cannot be changed also retains its data even
without power.
• RAM : Random Access Memory
• Also called read/write memory. This type of memory can have a program loaded and
then reloaded. It also loses its data with no power.

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Different ROM Chips
• Masked ROM :
• ROM that is programmed with data when fabricated. Data will not change once
installed. Hardwired.

• Programmable ROM (PROM) :

• Capable of being programmed by the user with a ROM programmer. Not hardwired.

• Erasable PROM (EPROM) :

• Much like the PROM this EPROM can be programmed and then erased by light.

• EEPROM :
• Another form of EPROM but is reprogammable electrically.

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Different RAM Chips

• Dynamic RAM (DRAM) :

• Leaky capacitors. Caps are charged and slowly leak until they are refreshed to there
original data locations. Ex. Computer RAM
• Static RAM (SRAM) :
• Much like a register. The contents stay valid and does not have to be refreshed. SRAM is
faster than DRAM but cost more Ex. Cache
• Each RAM chip has 2^n * m. n address inputs and m bidirectional data pins

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The operation of cache memory

1. Cache fetches data from 2. CPU checks to see

next to current addresses in whether the next instruction
main memory it requires is in cache

Cache
Main
Memory CPU
Memory
(SRAM)
(DRAM)
3. If it is, then the
4. If not, the CPU has to
instruction is fetched from
fetch next instruction from
the cache – a very fast
main memory - a much
position
slower process

= Bus connections
36
Addressing Modes

• Immediate
• Direct
• Indirect
• Register
• Register Indirect
• Displacement (Indexed)
• Stack

37
Immediate Addressing

• Operand is part of instruction

• Operand = address field
• e.g. ADD 5
• Add 5 to contents of accumulator
• 5 is operand
• No memory reference to fetch data
• Fast
• Limited range

38
Immediate Addressing Diagram

Instruction
Opcode Operand

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Direct Addressing
• Address field contains address of operand
• Effective address (EA) = address field (A)
• e.g. ADD A
• Add contents of cell A to accumulator
• Look in memory at address A for operand
• Single memory reference to access data
• No additional calculations to work out effective address
• Limited address space

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Direct Addressing Diagram

Instruction
Opcode Address A
Memory

Operand

41
Direct Addressing Diagram

Instruction
Opcode Address A
Memory

Operand

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Indirect Addressing (1)

• Memory cell pointed to by address field contains the address of

(pointer to) the operand
• EA = (A)
• Look in A, find address (A) and look there for operand
• e.g. ADD (A)
• Add contents of cell pointed to by contents of A to accumulator

43
Indirect Addressing (2)

• Large address space

• 2n where n = word length
• May be nested, multilevel, cascaded
• e.g. EA = (((A)))
• Draw the diagram yourself
• Multiple memory accesses to find operand
• Hence slower

44
 Indirect Addressing Diagram
Instruction
Opcode Address A
Memory

Pointer to operand

Operand

45
Register Addressing (1)

• Operand is held in register named in address filed

• EA = R
• Limited number of registers
• Very small address field needed
• Shorter instructions
• Faster instruction fetch

46
Register Addressing (2)

• No memory access
• Very fast execution
• Very limited address space
• Multiple registers helps performance
• Requires good assembly programming or compiler writing
• N.B. C programming
• register int a;
• c.f. Direct addressing

47
Register Addressing Diagram

Instruction
Opcode Register Address R
Registers

Operand

48
Register Indirect Addressing

• C.f. indirect addressing

• EA = (R)
• Operand is in memory cell pointed to by contents of register R
• Large address space (2n)
• One fewer memory access than indirect addressing

49
Register Indirect Addressing Diagram

Instruction
Opcode Register Address R
Memory

Registers

Pointer to Operand Operand

50
Displacement Addressing

• EA = A + (R)
• Address field hold two values
• A = base value
• R = register that holds displacement
• or vice versa

51
Displacement Addressing Diagram

Instruction
Opcode Register R Address A
Memory

Registers

Pointer to Operand + Operand

52
Relative Addressing

• A version of displacement addressing

• R = Program counter, PC
• EA = A + (PC)
• i.e. get operand from A cells from current location pointed to by PC
• c.f locality of reference & cache usage

53
Base-Register Addressing

• A holds displacement
• R holds pointer to base address
• R may be explicit or implicit
• e.g. segment registers in 80x86

54
Indexed Addressing

• A = base
• R = displacement
• EA = A + (R)
• Good for accessing arrays
• EA = A + (R)
• R++

55
Stack Addressing

• Operand is (implicitly) on top of stack

• e.g.
• ADD Pop top two items from stack and add

56
Input-Output Organization

• 11-1 Peripheral Devices

• I/O Subsystem
• Provides an efficient mode of communication between the central system and the
outside environment
• Peripheral (or I/O Device)
• Input or Output devices attached to the computer
• 11-2 Input-Output Interface
• 1) A conversion of signal values may be required

57
 • 2) A synchronization mechanism may be needed
• The data transfer rate of peripherals is usually slower than the transfer rate of the CPU
• 3) Data codes and formats in peripherals differ from the word format in the CPU and Memory
• 4) The operating modes of peripherals are different from each other
• Each peripherals must be controlled so as not to disturb the operation of other peripherals connected to the CPU
• Interface
• Special hardware components between the CPU and peripherals
• Supervise and Synchronize all input and output transfers

I/O bus
D ata
P rocessor A ddress
C ontrol

Interface Interface Interface Interface

Keyboard
and
display
P rinter
M agnetic
disk
M agnetic
tape
58
term inal
• Transfer
• Synchronous Data Transfer
• All data transfers occur simultaneously during the
occurrence of a clock pulse
• Registers in the interface share a common clock with CPU
registers
• Asynchronous Data Transfer
• Internal timing in each unit (CPU and Interface) is
independent
• Each unit uses its own private clock for internal registers

59
 Data bus Data bus
Source Destination Source Destination
unit Strobe unit unit Strobe unit

(a) Block diagram (a) Block diagram

Data  Valid data

Data
 Valid data

Strobe  Strobe 
(b) Timing diagram (b) Timing diagram

Fig. 11-3 Source- Fig. 11-4 Destination-

initiated strobe initiated strobe

60
 D ata bus Data bus

Source D ata valid D estination Source Data valid Destination

unit unit unit unit
D ata accepted Ready for data

(a) B lock diagram

(a) Block diagram

D ata
 Valid data

Ready for data



D ata valid 
• Handshake : Agreement betwee Data valid

D ata accepted  Data bus

 Valid data

(b) Tim ing diagram

(b) Tim ing diagram
Source unit D estination unit
Source unit Destination unit
P lace data on bus
Enable data valid. A ccept data from bus Ready to accept
Enable data accepted data.
Place data on bus Enable ready for data
Enable data valid.

D isable data valid

Invalidate data on bus D isable data accepted Accept data from bus
R eady to accept data Disable data valid Disable reday for data
(initial state) Invalidate data on bus
(initial state)
(c) Sequence of events
(c) Sequence of events

Fig. 11-5 Source-initiated handshake

Fig. 11-6 Destination-initiated handshak

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• 11-4 Modes of Transfer
Read status register
• Data transfer to and from peripherals
• 1) Programmed I/O Check flag bit

• 2) Interrupt-initiated I/O
• 3) Direct Memory Access (DMA) = 0
F la g

• 4) I/O Processor (IOP) = 1

Read data register

Interrupt-initiated I/O Transfer data to m em ory

• 1) Non-vectored : fixed branch address

• 2) Vectored : interrupt source supplies the branch address O p e ra tio n no
(interrupt vector) co m p le te ?

yes

Continue
w ith
program

62
• Polling
• Identify the highest-priority source by software means
• One common branch address is used for all interrupts
• Program polls the interrupt sources in sequence
• The highest-priority source is tested first
• Polling priority interrupt
• If there are many interrupt sources, the time required to poll them can exceed the time
available to service the I/O device
• 따라서 Hardware priority interrupt
• Daisy-Chaining :

P rocessor data bus

VA D 1 VA D 2 VA D 3

D evice 1 D evice 2 D evice 3

“1 “1 “0
To next
PI PO PI PO PI PO
D evice

” ” ”
Interrupt request
IN T
CPU
Interrupt acknow ledge
IN TA C K

63
 VA D

INTACK P riority in
Enable
PI
Vector address

INT P riority out

• One stageSof theQdaisy-chain
Interrupt
RF priority arrangement : Fig. 11-13 PO
request
from device PI RF PO Enable
R
0 0 0 0

 No interrupt request
O pen-collector
D elay
 0
1
1
0
0
1
0
0
 Invalid : interrupt
inverter request, but no acknowledge 
Interrupt request to C P U 1 1 1 1

 No interrupt request : Pass to other device (other device requested interrupt )

 Interrupt request

64
• Direct Memory Access (DMA)
• DMA
• DMA controller takes over the buses to manage the transfer directly between the I/O
device and memory

DBUS Address bus

BR BR High-im pedance
Bus request ABUS Data bus
DM A (disable)
CPU when BG is
Controller
RD Read enabled
BG BG
Bus grant WR W rite

65
• Transfer Modes
• 1) Burst transfer :
• 2) Cycle stealing transfer Address bus
• DMA Controller ( Intel 8237 DMAC )
• DMA Initialization Process
• 1) Set Address register :
• memory address for read/write Data bus Address bus
Data bus buffers
• 2) Set Word count register : buffers
• the number of words to transfer
• 3) Set transfer mode :
4) DMA transfer start :
• 5) EOT (End of Transfer) :
DMA select CS Address register

Internal bus
Register select RS
Read RD Word count register

Write WR
Control
Bus request BR logic Control register

Bus grant BG
DMA request
Interrupt Interrupt
to I/O device
DMA Acknowledge

66
• DMA Transfer (I/O to Memory)
• 1) I/O Device sends a DMA request
• 2) DMAC activates the BR line
• 3) CPU responds with BG line
• 4) DMAC sends a DMA acknowledge
Interrupt
to the I/O device BG Random access
CPU
• 5) I/O device puts a word in the data BR
memory (RAM)

bus (for memory write)

RD WR Address Data RD WR Address Data
• 6) DMAC write a data to the address
specified by Address register Read control
Write control
• 7) Decrement Word count register Data bus
• 8) Word count Address bus
• 9) Word count register
Address
select

RD WR Address Data
DMA acknowledge
DS
RS Direct memory I/O
access (DAM) Peripheral
BR controller device
DMA request
BG
Interrupt

67
• Input-Output Processor (IOP)
• IOP
• Communicate directly with all I/O devices
• Fetch and execute its own instruction
• IOP instructions are specifically designed to facilitate I/O transfer
• DMAC must be set up entirely by the CPU
• Designed to handle the details of I/O processing

Central Processing
unit (CPU)
Memory bus

Peripheral devices
Mem ory unit PD PD PD PD

Input-output
processor (IOP) I/O bus

68
• CPU - IOP Communication
• Memory units acts as a message center :
• each processor leaves information for the other

CPU operations IO P operations

Send instruction
Transfer status w ord
to test IO P path
to m em ory location

If status O K. , send
start I/O instruction Access m em ory for
to IO P IO P program

Conduct I/O transfer

CPU continues w ith
using DM A ; prepare
another program
status report

I/O transfer com pleted

interrupt CPU

Request IO P status

Transfer status w ord

to m em ory location
Check status w ord
for correct transfer

Continue

69
Input/output Devices

• Input/output devices are required for users to communicate with the

computer.
• In simple terms, input devices bring information INTO the computer
and output devices bring information OUT of a computer system.
These input/output devices are also known as peripherals.

70
Input Devices are:

• Keyboard
• Mouse
• Joystick
• Scanner
• Light Pen
• Touch Screen

71
\

Output devices are:

• Printers
• Plotters
• Monitor
• LCD

72
 Intel 8086/8088 Microprocessors
• Intel 8086 and 8088 Microprocessors are the basis of all IBM-PC
compatible computers
(8086 introduced in 1978, first IBM-PC released in 1981)
• All Intel, AMD and other advanced microprocessors are based on and
are compatible with the original 8086/8
• At Power Up and Reset time, Pentiums, Athlons etc all look like 8086
processors

73
Intel 8086/8088 Microprocessors

• Intel 8086 is a 16b microprocessor:

• 16b data registers, 16b ALU
• Width of external data bus:
• 8086: 16b
• 8088: 8b
• Width of external address bus: 16b+4b=20b
• Some techniques to optimise the CPU performance
when it’s executing programs
• Segment: Offset memory model
• Little-Endian Data Format
74
8086/8088

• Original IBM PC used 8088 microprocessor

• 8088 is similar to the 8086, but it has an external 8b
data bus & only 4B-deep queue
• For cost reduction reasons
• We can consider 8086 and 8088 together
• PC clones often used 8086 for better performance
• 8-bit bus reduces performance, but meant cheaper
computers

75
 8086/8088 Functional Units

Bus Interface
Unit(BIU)
Execution Unit
Fetches Opcodes,
(EU)
Reads Operands,
Writes Data

8086/8088 MPU
76
 8086/8088

• 8086/8088 consists of two internal units

• The execution unit (EU) - executes the instructions
• The bus interface unit (BIU) - fetches instructions, reads operands and writes results
• The 8086 has a 6B prefetch queue
• The 8088 has a 4B prefetch queue

77
8086/8088 Internal OrganisationEU BIU

Address Bus 20 bits

AH AL SUMMATION

BH BL
Data Bus

CH CL
CS
DH DL
DS
SP
SS
BP
ES
DI
IO
BI
Internal Bus
Communications Control
Registers
8088
Bus

Temporary
Registers

Instruction Queue

ALU
EU
Control
1 2 3 4

Flags

78
 BIU Elements
• Instruction Queue: the next instructions or data can be
fetched from memory while the processor is executing the
current instruction
• The memory interface is slower than the processor execution time so
this speeds up overall performance
• Segment Registers:
• CS, DS, SS and ES are 16b registers
• Used with the 16b Base registers to generate the 20b address
• Allow the 8086/8088 to address 1MB of memory
• Changed under program control to point to different segments as a
program executes
• Instruction Pointer (IP) contains the Offset Address of the next
instruction, the distance in bytes from the address given by
the current CS register

79
8086/8088 20-bit Addresses

CS

16-bit Segnment Base Address 0000

IP

16-bit Offset Address

20-bit Physical Address

80
 BIU Elements
• Instruction Queue: the next instructions or data can be
fetched from memory while the processor is executing the
current instruction
• The memory interface is slower than the processor execution time so
this speeds up overall performance
• Segment Registers:
• CS, DS, SS and ES are 16b registers
• Used with the 16b Base registers to generate the 20b address
• Allow the 8086/8088 to address 1MB of memory
• Changed under program control to point to different segments as a
program executes
• Instruction Pointer (IP) contains the Offset Address of the next
instruction, the distance in bytes from the address given by
the current CS register

81
 MAXIMUM MINIMUM
MODE MODE

GND 1 40 Vcc
AD14 AD15
AD13 A16,S3
AD12 A17,S4
AD11 A18,S5
AD10 A19,S6
AD9 /BHE,S7
AD8 MN,/MX
AD7 /RD
AD6 /RQ,/GT0 HOLD
AD5
8086 /RQ,/GT1 HLDA
AD4 /LOCK /WR
AD3 /S2 IO/M
AD2 /S1 DT/R
AD1 /S0 /DEN
AD0 QS0 ALE
NMI QS1 /INTA
INTR /TEST
CLK READY
GND 20 21 RESET

82
8086/8088 Summary

• First Generation (introduced June 1978)

• One of the first 16b processors on the market
• 16b internal registers
• 16/8b external data bus
• 20b address bus (1MB addressable)
• Used in 1st generation IBM PCs (1981)

83
• Thanks

84