Altera’s SoC Devices & Development

Tools
 A Complete Solutions Portfolio

Lowest Cost, Lowest Cost, Cost- and Power-Optimized Highest Bandwidth Lowest Risk,
Lowest Power Lowest Power FPGA FPGA Lowest Total Cost
CPLDs FPGA ASICs

MIPS Technology

Embedded FPGA
Hard & Soft Processors Intellectual Design Development
Property (IP) Software Kits
& Development Suites

2
2
SoC System Architecture Hard Processor System (HPS)
 Processor ARM Cortex-A9
NEON / FPU
ARM Cortex-A9
NEON / FPU
USB
OTG
Ethernet
(x2) (1)
L1 Cache L1 Cache (x2) (1)
- Dual-core ARM® Cortex™-A9 MP Core™
processor L2 Cache GPIO
I2C
(x2)
(x4)

HPS I/Os
- 4,000 MIPS (up to 800 MHz per core)
QSPI JTAG
- NEON coprocessor with double-precision FPU Flash
64-KB
Debug /
SPI CAN
RAM (x2)
(x4) (x2)
Control Trace (1)
- Rich set of embedded peripherals
NAND SD /
Timers DMA UART
- 32-KB/32-KB L1 caches per core Flash SDIO/
(x11) (8 Channels) (x2)
(1) (2)
MMC (1)
- 512-KB shared L2 cache
FPGA
Shared Multiport DDR HPS to FPGA
Configu
SDRAM Controller (2) FPGA to HPS
ration
 Multiport SDRAM controller
- Up to 533-MHz DDR3 and LPDDR2*

FPGA General Purpose I/Os

• 28LP process
- Up to 400-MHz DDR2 • 8-input ALMs
• Variable-precision
- Integrated ECC support FPGA •
DSP
M10K memory and
640-bit MLABs
- Cache coherency between ARM & FPGA IP
• fPLLs

 High-bandwidth on-chip interfaces

Hard Multiport DDR Hard 3-, 5-, 6-,
Multiport
Multiport DDR
DDRSDRAM
SDRAM
- > 125-Gbps HPS-to-FPGA interface SDRAM Controller
Controller
(2) PCIe
PCIe and 10-Gbps
Controller Transceivers
- > 125-Gbps FPGA-to-SDRAM interface
Notes:
* LPDDR2 support coming (1) Integrated direct memory access (DMA)
(2) Integrated ECC

3 3
 SoC Software Development Tools
 Software Development Tools
- Altera’s SoC Embedded Development Suite (EDS)
 GNU Tools, Utilities, Libraries
 ARM Design Studio 5 (DS-5)
 Altera – Exclusive FPGA Adaptive
- Lauterbach TRACE32
- Wind River Workbench
- ENEA Optima

4 4
Embedded SW Availability

Development
Vendor OS/RTOS Availability
Tools
Open Source Linux 3.7 Linaro compiler Now through Altera
Wind River Systems VxWorks 6.9.2 Workbench 3.3.2 Q2 2013 (beta now)
Micriµm µC/OS-II, µC/OS-III GNU compiler Q2 2013 (beta now)
Enea OSE 5.5.3 Optima 2.6 Q2 2013 (beta now)
Express Logic ThreadX 5.5.3 GNU compiler Q2 2013 (June)
Wind River Systems Wind River Linux 5 Workbench/GNU Q2 2013 (June-Wind River EAR)
QNX QNX/Neutrino 6.5.3 Momentics Q3 2013 (July)
Fujisoft Android GNU compiler Q2 2013 (June)
Green Hills INTEGRITY Multi/Green Hills Q3 2013 (July)
Windows Embedded
Microsoft Microsoft/Studio Q3 2013 (August)
7

5 5
Arrow’s SoCkit Overview
Arrow’s SoCkit Development Board
Based on:
Cyclone V SoC FPGA

7
Arrow Cyclone V SoCKit

Button Switch x8

8
Golden Reference Design
 HPS configuration
- DRAM, QSPI, SD/Card
- All peripheral functions
exposed at least once

 FPGA configuration
- Simple Qsys “sandbox”
system
 First experience in ARM /
FPGA integration
- Getting started guide to walk
them through the process on
integrating IP
 HW simulation
 Verification via system
console
 Verification via CPU
 HW/SW hand-off

9
 Arrow’s SoCkit Dev Board – HW Features
 Cyclone V SOC FPGA
 Compact Board Size: ~15x10 cm (6” x 4”)
 ARM Cortex-A9 based Hard Processor System (HPS)
 Full set of peripherals (Flash I/F’s, GbE, USB, SD, SPI, I2C, CAN, UARTs, DMA’s, Timers…)

 Two independent banks of DDR3: 4GB (x32) @ 533MHz

 GbE Ethernet
 USB 2.0
 OTG
 UART to USB

 SD Card Socket (Support 4-bit SD mode)

 Display
 24-bits RGB VGA
 Graphic LCD: 128x64

10 10
Arrow’s SoCkit Dev Board – HW Features (2)
 General Peripheral: LEDs / Buttons / Switches / IR
 Audio CODEC: Line-In, Line-Out, Mic-In
 Temperature Sensor
 G-Sensor
 On-Board USB-Blaster II (Config/Debug cable interface)
 Expansion Headers
 HPS IP: LTC (Linear Tech) Header

 FPGA fabric: High Speed Mezzanine Connector (HSMC) including transceivers

Note: For Mictor Dstream connectors – see the Altera SoC Dev kit

11 11
Altera’s SoC Embedded Design Suite
(SoC EDS)
Altera SoC Embedded Design Suite
Comprehensive Suite of SW Dev Tools:
 Hardware / Software Handoff Tools
- Preloader Generator: Parameterizes files for Preloader/BSP
- Device Tree Builder (Linux) (13.0 SP1)

 Driver Development, Board Bring-up

 Bare-metal application development
- SoC Hardware Libraries
- Bare-metal compiler tools Altera
Exclusive SoC EDS
 FPGA-adaptive debugging
- ARM DS-5 Altera Edition Toolkit
- Seamless FPGA peripheral visibility

 Linux application development

- Yocto Linux build environment
- Pre-built binaries for Linux / U-Boot
- Work in conjunction with the Community Portal
Unprecedented Visibility and Debug Capability!
 Design examples

13 13
 SoC EDS Contents
Web Subscription 30-Day
Component Key Feature
Edition Edition Evaluation
Hardware/Software
Preloader Image Generator x x x
Handoff Tools
Flash Image Creator x x x
Device Tree Generator (Linux) x x x
ARM DS-5 Altera
Eclipse IDE x x x
Edition
Debugging over Ethernet (Linux) x x x
Debugging over USB-Blaster II JTAG x x
Automatic FPGA Register Views x x
Hardware Cross-triggering x x
CPU/FPGA Event Correlation x x
Compilers Linaro Tool Chain (Linux) x x x
CodeBench Lite EABI (Bare-metal) x x x
Hardware Libraries Bare-metal programming Support x x x
SoC Programming
Golden System Reference Design x x x
Examples

* Not available in 13.0

14 14
 Altera SoC EDS Additional Deliverables
 Golden Hardware Reference Design (GHRD)
 Pre-built: Linux Kernel, Root FileSystem, U-Boot
- Pre-built with full source (Linux snapshot)
- Link to community website for updates

 Software Example Designs:

- Hello World Bare metal (GNU)
- Hello World Bare metal (armcc)
- Hello World for Application Linux
- Linux simple device driver example design
- Linux Web Server simple driver

15 15
 Software Process: HPS Boot Stages
Boot ROM code
• Hardened by Altera into device.
• Scans boot select pins to determine clocks/boot
source
Reset - NAND, QSPI, SD/MMC, FPGA or On-chip RAM
• Sets up PLL’s if selected by clock pins
• Configure minimal set of HPS I/O pins to read flash SW / FW
• Performs CRC checking & loads ISW into On-Chip
Developer’s
Boot ROM RAM
PreLoader (Initial Software) efforts
• Altera Reference code + generated system .c & .h
files
• Runs from On-Chip memory
PreLoader • Configures scan manager with pin configuration data
• Initializes and calibrates SDRAM
• Loads Boot Loader code into SDRAM
Boot Loader
Boot Loader • Application / OS specific
• Altera provides U-Boot as a reference example

Operating System
OS • Linux, VxWorks, OSE, etc
• Device drivers and BSP
• Root FileSystem

Application
User Application
• IDE and Debug
• FPGA configuration

16 16
 Hardware-Software Handoff: PreLoader Generator
Generates & Parameterizes files for making the PreLoader / BSP
Reset
Hard coded in HPS

Boot ROM
PreLoader “Initial Software (ISW)” or
“Secondary Program Loader (SPL)”
• Low level hardware-centric source code
PreLoader • Runs from On-Chip memory
• Configures scan manager with pin configuration data
• Initializes and calibrates SDRAM
• Loads Boot Loader code into SDRAM
Boot Loader

uBoot - common bootloader – popular for Linux

OS

Application

17 17
 SoC Boot Phases to Bare-metal or OS
Recommended Flow

Typical OS Boot Preloader Bootloader OS Application

Boot Process ROM

Bare-Metal Boot Preloader Bootloader Bare-Metal

Application ROM Application

Bare-Metal Boot Preloader Bare-Metal

Application ROM Application

Bare-Metal Boot Bare-Metal

Preloader ROM Application
Replacement

Boot Phase Boot ROM | Preloader | Bootloader | OS | Apps

18 18
 HW Libraries & OS/Bare-Metal Development
 Bare-metal
- No Operating System

- User code and hardware libraries/drivers Bare-metal App

Application Bare-
 Hardware Libraries Operating metal
- Software interface to all system registers System App
- Functions to configure some basic system
operations
BSP
(e.g. clock speed settings, cache settings, HWLIB
FPGA configuration, etc.) Hardware
- Support board bring-up and diagnostics Libraries
- Can be used by bare-metal application, device
drivers, or RTOS
HPS
 GNU-based bare-metal (EABI)
compiler tools

19 19
APIs in HWLIB (Bare-metal) Phase 1 Phase 2
(V13.1)

MPU Subsystem Timers Test Support Mgmt Cache Mgmt

UART

Memory Map Cntl Watchdog ECC/Parity Error UART

Address Filters General Purpose Basic Mem Tests JTAG UART

Mem Coherence
Bridge Management Flash Memory Intrf

FPGA Manager FPGA2HPS QSPI MMU Mgmt

Full Configuration HPS2FPGA NAND Interrupt Ctrl

Partial Reconfig LWHPS2FPGA SD/MMC
Pin I/O Cnf Mgmt

Clock Manager System Manager GPIO ECC Mgmt

Reset Manager SDRAM Ctrl DMA Parity Mgmt

SoCAL Layer (non ARM IP) SoCAL Layer (ARM IP)

20 20
SoC EDS Includes ARM DS-5 Altera Edition
 Industry’s most advanced multicore
debugger from ARM for ARM processors
 Supports JTAG/Ethernet/Trace debug in
one package
 Trace pod – Dstream – 4Gbyte trace
memory
 True dual core/debugger capability
 Streamline: Statistical analysis of
software load and bus traffic spanning
the CPUs and FPGA under Linux
 Integrated OS-aware analysis
and debug capability
 Yocto plugin to enable
Linux based application development

21 21
 One Device, Two Debugging Tools?
ARM® DS-5™ Toolkit Altera Quartus™ II Software

JTAG
DSTREAM™

 Dedicated JTAG connection JTAG

 Visualize & control CPU  Dedicated JTAG connection
subsystem
 Visualize & control FPGA

22 22
 One Device, Two Debugging Tools?
ARM® DS-5™ Toolkit Altera Quartus™ II Software

Deb u g g in g
Barrier
a b le to v is ualize
 No single
tool/c
tr o l b o th C PU and
a nd c on
P G A d o m ains
F F P G A to
a n d
w a y for CPU
JTAG
 N o
g e r a n d c orrelate
DSTREAM ™
cross trig s o ftw a r e events
h a r d w a r e and
 Dedicated JTAG connection
e b u g g e r c an JTAG
 No “fixed
”d
Visualize & control CPU
e ds o f

e s s t h e n e  Dedicated JTAG connection
subsystem a dd r P G A h a r dwareVisualize & control FPGA
F
“changing”

23 23
 Familiar Eclipse Framework
Select
Perspective

File Outline View

Viewer (View functions,
enums, classes,
structs etc.)

Project
s

Terminal
Window

24 24
 DS-5 Altera Edition
Productivity-Boosting Features
 Single USB-Blaster target connection
for software and hardware debug
 Automatic creation of register views
of FPGA peripherals
 Hardware cross-triggering between the CPU and FPGA
ONLY SoC Technology… Altera’s SoC’s can achieve this
domains
 Non-intrusive trace of CPU software instructions correlated
with application events and FPGA hardware events
 Simultaneous debug and trace for Cortex-A9 cores AND
cores synthesized on FPGA*
 Streamline support: Statistical analysis of software load
and* For
bus traffic-compliant
CoreSight
™ spanning cores: IPthe CPUs
added and
using proper FPGA
handoff files (CMSIS)

25 25
 Altera SoC EDS - Key Benefits
 Faster time to market, lower development costs
 Covers full software development flow for Altera SoC
devices
 All necessary tools and examples in one package to
enable rapid start for developers
 Provides software debug views of full SoC by adapting to
changing FPGA designs (Subscription)
 Unprecedented visibility and control across
processor cores and across CPU, FPGA domains
 OEM packing ensures ease of licensing and ease of use

26 26
Software Debug & Trace
Interfaces & Tools
 Interfaces for SW Developers
Flash / QSPI / SD

SW tools Ethernet
Host Machine

Bottom side
SD

Trace

Today’s workshop JTAG via USB

JTAG

28 28
 Software Debug Interfaces
 JTAG
- Direct connection to hardware
- Halts processor, can master system via control of processor
- Debug any code at low level – driver, OS kernel, bare metal application
- OS aware debugger display optional
Note: Other debuggers require 2 debugger interfaces for dual-core processors

 Ethernet
- Requires running software to drive it
- Processor/OS cannot be halted
- OS Application can be halted
- Good for high level programming (fast, easy)
- Debuggers usually have OS aware GUIs and features
- Cannot do low level debug (kernel, driver, bare metal) as OS cannot be
stopped

29 29
Real-Time Trace (JTAG/Ethernet/USB)
 Processor ‘data logger’ system
 Runs at full speed to identify and debug real-time software issues
 Hardware triggers on predefined condition
- Address value, data value or a combination
 Stores instruction or data flow information to on-chip or off-chip memory for
analysis in debugger

Trace Capable Debugger

Host
Display High-speed
Trace Pod with Connection
on-board memory (i.e. Mictor conn)
Processor
Ethernet or USB Processor
Trace HW
JTAG/USB/Ethernet

30
SoC Development Flow

Software Design Flow – Part 1: Preloader and Bare metal

 Software Perspective
Application
 Application M
id
Software Engineer
dl

Middleware
e


W
a
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e

O
 Hardware BS
DS Firmware
abstraction SrP
Software Engineer
oHi
CWv
RALe
r
SeLi
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lPi(
i sL
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32 32
 System Development Flow
FPGA Design Flow Software Design Flow
Hardware Software
Development Development

• ARM Development Studio

• Quartus II design software
5
• Qsys system integration
• GNU toolchain
tool Design Design • OS/BSP: Linux, VxWorks
• Standard RTL flow
• Hardware Libraries
• Altera and partner IP
• Design Examples

• ModelSim, VCS, NCSim, etc.

• AMBA-AXI and Avalon bus Simulate Simulate • Virtual Target
functional models (BFMs)

• SignalTap™ II logic
• GNU, Lauterbach, DS5
analyzer Debug Debug
• System Console

• Quartus II Programmer
• In-system Update
Release Release • Flash Programmer

33
System Development Flow
FPGA Design Flow Software Design Flow
Hardware Software
Development Development

• ARM Development Studio

• Quartus II design software
5
• Qsys system integration
HW/SW • GNU toolchain
tool Design Design • OS/BSP: Linux, VxWorks
• Standard RTL flow Handoff
• Hardware Libraries
• Altera and partner IP
• Design Examples

• ModelSim,etc.
• AMBA-AXI and Avalon bus Simulate Simulate • Software
Virtual Target
functional models (BFMs)
Development
• SignalTap™ II logic
• GNU, Lauterbach, DS5
analyzer Debug Debug
• System Console

• Quartus II Programmer
• In-system Update
Release Release • Flash Programmer

34
 Quick Summary
 FPGA:
- Looks like a FPGA
- Works like a FPGA
- Standard FPGA development flow
- Quartus II, Qsys, SignalTap, System Console, USB blaster...

 ARM HPS:
- Looks like an ARM processor system
- Works like an ARM processor system
- Standard ARM development flow
- ARM Cortex-A9 compiler/debugger, JTAG tools, program trace...

Back
35 35
 Software Process: HPS Boot Stages
Boot ROM code
• Hardened by Altera into device.
• Scans boot select pins to determine clocks/boot
source
Reset - NAND, QSPI, SD/MMC, FPGA or On-chip RAM
• Sets up PLL’s if selected by clock pins
• Configure minimal set of HPS I/O pins to read flash SW / FW
• Performs CRC checking & loads ISW into On-Chip
Developer’s
Boot ROM RAM
PreLoader (Initial Software) efforts
• Altera Reference code + generated system .c & .h
files
• Runs from On-Chip memory
PreLoader • Configures scan manager with pin configuration data
• Initializes and calibrates SDRAM
• Loads Boot Loader code into SDRAM
Boot Loader
Boot Loader • Application / OS specific
• Altera provides U-Boot as a reference example

Operating System
OS • Linux, VxWorks, OSE, etc
• Device drivers and BSP
• Root FileSystem

Application
User Application
• IDE and Debug
• FPGA configuration

36 36
 Hardware / Software Handoff Tools

 Allows hardware and software teams to work

‘independently’ and follow their familiar
design flows

 Altera Quartus II / Qsys handoff output files

converted into files for the software design
flow

 Device Tree standard specifies hardware

configuration/peripherals so that Linux kernel
can boot up correctly

37 37
 Hardware / Software Handoff
Qsys system info, SDRAM calibration files,
ID / timestamp, HPS IOCSR data
Hardware

ISW_handoff.sys system.sopcinfo

Preloader Device Tree

Generator Generator

User
Options

.c & .h Linux
Software source files Device Tree

38 38
Hardware/Software Design Flow Overview
PreLoader
Settings Handoff
Directory files

Preloader
Handoff Preloader
Generator

DS-5
HW Design ACDS .svd Debugger

DeviceTree
.sopcinfo Device Tree
Generator
For
SoC EDS Linux

.sof

39 39
Hardware/Software Design Flow Overview
Eclipse/GCC/GDB Software Design Flow
Hardware Software
Development Development

Open New
BSP Project

Import
HW/SW
HW/SW
Handoff files
Handoff Files

Preloader Enter User

Generator Settings

Build
Flash
Programmer

Software Flash Image

SOF/POF
Image builder

40
Design Areas on SoC FPGA Devices

Processor System
The domain of software engineers

Problem areas

• Identification of HW issues at runtime

• Working across SW & HW domains
• Coherent real-time HW/SW debug
• Drivers for new or changing hardware
• System-level performance analysis

FPGA Fabric
The domain of hardware engineers

41
Altera SoC FPGA Based Peripherals
FPGA MEMORY MAP
FPGA IP mapped
To 3GB and above

FPGA IP

32/64/128-bit AXI
AXI (LW)
AXI
AXI

Bridges plus
Lightweight Bridge
32-bit
L3 interconnect

L2 Cache

Cortex-A9 Cortex-A9
Cortex-A9 0-3(+)GB
memory space
HPS

42
 Cortex-A9 Debug
 Interactive Debug
- Controlled via JTAG or CPU monitor code
- 6 HW Breakpoints, 2 with Context ID compare
- 4 HW Watchpoints

 Performance Monitoring
- Each A9 has a Performance Monitoring Unit (PMU)
- Each PMU can monitor 58 different events
 6 counters to count events
 Events may be triggers or put in trace

 See Cortex A9 TRM for additional details

Back
43 43
Visualization of SoC FPGA Peripherals –
FPGA Adaptive
 Register views assist the debug of FPGA
peripherals
- File generated by FPGA tool flow
- Automatically imported in
DS-5 Debugger
- Changes dynamically

 Debug views to debug

software drivers
- Self-documenting
- Grouped by peripheral,
register and bit-field

CMSIS

Peripheral register
descriptions

44
 Altera SoC Debug Architecture STM: System trace module
PTM: Proc trace module
TPIU: Trace port I/F Unit
28 HW signal events CTI: Cross trigger I/F
injected into trace stream FPGA CTM: Cross trigger module
DAP: Debug Access Port
FPGA IP
Trace
Cross-triggers between CPUs and
FPGA(8) and CPUs (8) CoreSight compatible IP
SWD/ implemented in FPGA logic
JTAG accessible from Debugger

CTI
DAP

Debug bus
TMC
STM Trace bus
ETR
Export trace
System bus

CTM to trace port,

Mictor Connector
peripheral or
PTM PTM memory
Full trace capability on
hardened part of the SoC Ability to inject FPGA TPIU
hardware debug data into
the CoreSight trace stream
CTI Cortex-A9 CTI Cortex-A9
Infrastructure to trace
CPUs synthesized on HPS
the FPGA

45
System-Level
Performance Analysis
 Performance
bottlenecks in SoCs ARM® DS-5™ Streamline
often come from the Linux OS Counters
CPU interaction with
the rest of the SoC
Processor Counters,
 Streamline visualizes Aggregated, or Per Core
software activity with
performance counters
Power Consumption
from the SoC and
FPGA to enable full FPGA Block Counters
system-level analysis
 Streamline only Process/Thread Heat Map
requires a TCP/IP
connection to the SoC Application Events

46
Synthesizing CPUs on FPGA
 CPUs and CoreSight compatible IP synthesized on the FPGA are
accessible via the Debug Access Port (DAP) and therefore detectable
and debuggable by DS-5
DSP

IP
FPGA

SWD/
JTAG
DAP Debug
bus
Cortex-A9

Cortex-A9
HPS

47
Key Benefits for Developers
Removes Debugging Barrier!
 Faster time to market,
lower development costs
 Significant productivity gains
 Provides software debug views
of full SoC by adapting to changing FPGA designs
 Unprecedented visibility and control across
processor cores and across CPU, FPGA domains
 Standard, widely used, familiar DS-5 user interface
provides SW engineers with rapid starts
 OEM packing ensures ease of licensing and ease of use
48 48
Embedded Linux for SoC

Software Design Flow – Part 2

 Getting to the familiar Linux Boot

50 50
 SoC Linux: Key Takeaways
 Linux & tools available for SoC
 One of the first ARM multi-vendor platforms
supported by a single Linux Kernel v3.7
 Leverages new, efficient community
methodology for generating custom Linux
distributions - Yocto
 Innovation on Device Tree to support
“changing” hardware profile
- Device Tree Generator (DTG), available v13.0 SP1

 Community Portal to facilitate collaboration

with developers
 Kernel, U-Boot up-streamed and maintained

51 51
 Linux for SoC: Innovative Approach
 We discussed the low level hardware handoff:

 Typically developers build Linux for fixed form chips

 The SoC Challenge...
How do you build Linux for a chip that changes?

You use a “Device Tree Generator”, of course!

52 52
What’s a Linux Device Tree?
 A Data Structure for describing hardware

 Enables Device Drivers to be linked to Linux kernel at run-

time
- No Linux kernel recompile required
- Drivers loaded dynamically after loading Device Tree
- Device Tree embedded in FPGA memory, correct drivers are always loaded
- Can carry additional system information

53
 Device Tree Generator

Altera SoC
Embedded Design Suite
Directory

Device Device Tree Source DTS

Tree
Compiler
Generator De
vi
ce
Tr
e e
Bl
o b

Board/User Info

Device Tree Generator Ships in Altera SoC

Embedded Design Suite – in V13.0 SP1
SD/MMC

54 54
 Why Use a Device Tree?
 Single compiled kernel and set of drivers used on a
number of boards
 Key with FPGA’s where hardware is easily and
frequently changed
 Facilitates changing hardware on the fly
 Dynamic Device Tree
- Ability to update your FPGA/Device Tree Source without rebooting the
kernel
- Available soon

55 55
SoC Linux Board Support Package
 U-Boot (not pictured)
 Kernel User Space
(debug, compiler, shell, applications etc)
 Drivers for SoC
 Drivers for the board BSP
components Kernel
 SoC specific layer
Drivers
 Source code for the root
file system Machine Specific Layer

 Build environment
SoC
SoC Linux BSP release provides Board
all of the components in source
code form

56 56
 What is Yocto?
 As stated by the project page:
The Yocto Project™ is an open source collaboration project that
provides templates, tools and methods to help you create custom
Linux-based systems for embedded products regardless of the
hardware architecture.

 Yocto is based on Open Embedded (OE)

- Suite of tools (e.g. bitbake)
- Leverages OE’s architecture
 Recipes, layers
- Makes sure the various components required by OE work
together

57 57
 Benefits of Yocto Project
 Less time spent on things which don’t add value
(build system, core Linux components)
 Increased ability to enable key silicon features
 Transparent Upstream changes
 Vibrant Developer Community
 Start with a validated collection of software (tool
chain, kernel, user space).
 Easy transition to a commercial embedded Linux

"It’s not an embedded distribution

- it creates a custom one for you.“
- Yocto Project

58 58
 How does Altera use Yocto?
 Added SoC FPGA layer to Yocto

 Built source code for our BSP

- Kernel, U-Boot and Root File System

 Built the Tool Chain

- GCC, built by Yocto from sources
- Provide pre-built tool chains to reduce build
time in the near future.

59 59
 Linux Software Development Workflow
Target
Portal
Host Machine

Router

Start Console BootROM

Window Stored in on-chipROM

Start Browser go Preloader

Stored in flash, runs from
to Portal
SDRAM

Portal Clone git Trees U-Boot

kernel, U-Boot, Tool Chain Stored in flash, runs from
SDRAM

Develop Linux Kernel

Stored in flash/network, runs
Application from SDRAM

Build Image Run Application

(Flash/SD/QSPI)

Binaries come pre-built in the SoC EDS

60 60
 Boot Image & Flash Image
Boot Image storage location
Preloader : SD/MMC, QSPI, NAND, FPGA
U-Boot : SD/MMC, QSPI, NAND
Linux : SD/MMC, QSPI, NAND, mass storage, network via
tftp, remote PC via UART

Flash Image content

1. Preloader images 5. Root file system
2. U-Boot images 6. FPGA POF file
3. uImage (Linux) 7. Applications
8. User / Application files
4. Device Tree Blob

Note: EDS doesn’t contain tool to program SD/MMC. Use Linux or

Windows tools as shown in appendix. For all other Flash devices, use
HPS flash programmer

61 61
Altera SoC Linux: Key Features and Benefits
Feature Benefit
Yocto Standard Build System
Adapts software to changing
Device Tree Generator
hardware

Prebuilt Binaries (EDS) Save time to evaluate boards

Latest Stable Kernel Latest bug fixes, features,

(Kernel.org) security patches

Key Presence in Linux Optimal support & design

Community resources
Confidence in your Linux
Altera a designated Maintainer
source: compatibility, longevity

62 62
Advanced Debug
Cross-Domain Debug 1
 Trigger from software world to FPGA world
SOFTWARE TRIGGER
OR BREAKPOINT TRIGGER

HARDWARE TRIGGER!

64
Cross-Domain Debug 2
 Trigger from FPGA world to software world

HARDWARE TRIGGER

EXECUTION STOP SW TRACE TRIGGER!

65
 Correlate HW and SW Events

 Debug event ARM® DS-5™ Toolkit

trigger point set
from either
SignalTap™ II
Logic Analyzer or
DS-5 debugger
Timestamp
Correlated
 Designers can
then analyze the SignalTap II Logic Analyzer

captured trace and

timestamp-
correlated events

66 66
Cross-Domain Debug 3
 Exploiting the power of CoreSight trace

PTM

CPUs Timestamp

STM

Timestamp
28 FPGA
Events STM

Global
timestamp BREAKING THROUGH THE DEBUG BARRIER!
unit

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Altera and the Linux Community
 Open Source

Code
Repository

Code
Founders
Repository
/ Admin

Community Founders
/ Admin

69 69
 Linux Distribution

Linux OS Utilities

SW
Kernel.org Busybox.net
Development Applications
Tools

GNU.org x.org

Linux Build
Distribution Tools

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Altera in the Linux Community
 Altera awarded maintainership for the
‘SoC FPGA’ architecture Open Source Community
Kernel.org, U-Boot, Yocto, Android
- Kernel (arch/arm/mach-socfpga)
- U-Boot (altera/socfpga_cyclone5)
upstream

 Being a maintainer means

- Upstream the SoC related code
- Control the changes against the SoC Maintainer
code requested by the community
Public
 SoC FPGA is 1 of the 5 ARM platforms Repo/git
included in Kernel v3.7
- Build one kernel that contains support
for 5 ARM platforms
Customers & Partners
Contributors

71 71
 Software Delivery
 SoC Embedded Development Suite (EDS) will be shipped
with the Altera ACDS distribution (Quartus II, etc.)
- Stand alone install

 The Portal site RocketBoards.org will host the SoC Linux

GIT server to deliver upgrades, patches, etc.

 Commercial OS vendors will distribute through their normal

channels

72 72
 Welcome to the RocketBoards.org!
http://rocketboards.org

•Existing developer starts

Alter here
•Silicon
•Boards
a.co •Soft IP
•Major Linux release

m •SDK
•Static docs
rock •Forum •
New developer
etbo starts here
•FOSWiki
ards. •Links to partners
org •Dynamic Docs
•gitweb
git.roc •Frequent Updates
ketbo •Project
ards.o Repositories
•Kernel Repository
rg
•U-Boot Repository

lists.r •Mailman
ocket •Support
board •Mail list
s.org
server
Linux Portal
One User Experience

73 73
Coordinated Multi-Channel Delivery

QII SoC EDS

.org

Altera.com Altera.com RocketBoards.org Partners

Major Releases Prebuilt Binaries: Source for Kernel OSs

Binaries of Kernel ,U-Boot, U-Boot & Yocto BSPs
Kernel, U-Boot, Tools, yocto, Updates
Yocto, RFS Minimal RFS Patches Middleware
GNU Toolchain Public GIT
Source for 3rd Party Tools
Kernel, U-Boot Eclipse IDE Wiki
Yocto, min. RFS, Libraries/APIs Forum
SoC Tools List Server Support
GNU Toolchain
Sample Apps
Documentation GHRD, Drivers Market place Design Services
Ref Designs Partner centre

74 74
 Linux Mainline Release Cycle
~Weeks: 0 ~12 Weeks ~24 Weeks

v3.8 Development v3.9 Development

Mainline
Kernel
Development v3.7 rc1 rcn
v3.8 rc1 rcn
v3.9 rc1
Branch
(Kernel.org)
Merge Merge Merge
Stabilization Stabilization
Window Window Window

Community
Accepted New No New Features New No New Features
New
Features
Code & Features Bug Fix Only Features Bug Fix Only
Altera
Upstream

75 75
 Altera Linux Executive Summary
 Altera always moves to the latest kernel version
(~3 months) – See Addendum release cycle info

 Altera maintains the Linux SoC architecture and upstreams to the

very latest kernel
(development branch)

 Community focus on branch maintenance

 For maintenance of older kernels/branches, customers must work

with Linux partners

 Common strategy (eg. TI, Freescale, etc)

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 Linux Availability Summary

 Mainline kernel version – kernel.org/EDS

 Development version of mainline kernel – Kernel.org

 Community maintained Branches – Altera GIT server

 Update and patches - Altera GIT server

77 77
Resources & Next Steps
-Training
-Altera’sCyclone V SoC Development Kit
-Links & Support
-Next Steps
 Altera SoC Dev Kit Contents
 FPGA Design Software:
- Quartus II Web Edition, ModelSim (Altera Starter Ed)
- Golden Hardware Reference Design

 Software Development Development tools (EDS):

- GNU tools, Eclipse IDE, ARM DS-5 Debugger
- Linux distribution & full BSP
- Altera HW lib (APIs for Altera “manager” IP)

 Out-of-Box Experience
- Web Server (Linux) Application
 Links to resources web resources
(documentation & downloads)
 Board update portal
- Board test system (board HW verification)
- Golden HW reference design (getting started)
- Web portal for one-stop Embedded SW download

79 79
Altera’s Dev Kit: Golden Reference Design

 HPS configuration ARM A9

NEON/FPU
ARM A9
NEON/FPU DDR/SDRAM

- DRAM, QSPI, SD/Card I$ D$ I$ D$

- All peripheral functions exposed at L2$

least once TMC/Trace QSPI

- Drivers USB OTG GPIO

USB OTG I 2C
 HAL Ethernet I 2C
 Linux Ethernet UART
SD/MMC ROM UART
 FPGA configuration NAND flash SPI
RAM 64KB SPI
- Simple Qsys “sandbox” system CAN
FPGA mngr
 First experience in ARM / FPGA CAN
DMA
integration TIMERS

- Getting started guide to walk them

through the process integrating IP HPS HPS► FPGA
HPS► FPGA
Low latency
FPGA►HPS

 HW simulation
 Verification via system console FPGA JTAG
Master
 Verification via CPU Memory SYSID

PIO
 HW/SW hand-off
PIO

80
 Resources, Links & Support
 SoC Altera.com Site here
 Altera Dev Tools
- Quartus II Design Suite – includes Qsys
- Quartus II Literature, Handbook, etc.
- SoC Embedded Design Suite (EDS)
- Design Software & Download Center Sites
 ARM Dev Tools
- DS-5 Altera Edition
- www.arm.com , ARM SW dev tools
 Altera Forum Community: www.alteraforum.com
 Altera Wiki Community: www.alterawiki.com
 SoC / Linux Web Portal: http://rocketboards.org
 Support info & Links
- Altera’s MySupport – for submitting Service Requests – GO SIGN UP!
- Altera’s Design Resources Site

81 81