The Memory System

Fundamental Concepts
 Some basic concepts
• Maximum size of the Main Memory
• byte-addressable
• CPU-Main Memory Connection
Processor Memory
k-bit
address bus
MAR
n-bit
data bus Up to 2 k addressable
MDR locations

Word length = n bits

Control lines
( R / W, MFC, etc.)
 Some basic concepts(Contd.,)
Measures for the speed of a memory:
 memory access time.
 memory cycle time.
An important design issue is to provide a
computer system with as large and fast a
memory as possible, within a given cost
target.
Several techniques to increase the effective
size and speed of the memory:
 Cache memory (to increase the effective speed).
 Virtual memory (to increase the effective size).
 Speed, Size, and Cost
 A big challenge in the design of a computer system
is to provide a sufficiently large memory, with a
reasonable speed at an affordable cost.
 Static RAM:
 Very fast, but expensive, because a basic SRAM cell has a complex circuit making it
impossible to pack a large number of cells onto a single chip.
 Dynamic RAM:
 Simpler basic cell circuit, hence are much less expensive, but significantly slower than
SRAMs.
 Magnetic disks:
 Storage provided by DRAMs is higher than SRAMs, but is still less than what is
necessary.
 Secondary storage such as magnetic disks provide a large amount
of storage, but is much slower than DRAMs.
Memory Hierarchy
 Memory Hierarchy
Processor •Fastest access is to the data held in
processor registers. Registers are at
Registers the top of the memory hierarchy.
•
Increasing Increasing Increasing Relatively small amount of memory that
size speed cost per bit can be implemented on the processor
Primary L1
cache chip. This is processor cache.
•Two levels of cache. Level 1 (L1) cache
is on the processor chip. Level 2 (L2)
cache is in between main memory and
Secondary L2 processor.
cache
•Next level is main memory, implemented
as SIMMs. Much larger, but much slower
than cache memory.
Main •Next level is magnetic disks. Huge amount
memory of inexepensive storage.
•Speed of memory access is critical, the
idea is to bring instructions and data
Magnetic disk
that will be used in the near future as
secondary close to the processor as possible.
memory
The Memory System

Cache Memories
 Cache Memories
• Processor is much faster than the main memory.
– As a result, the processor has to spend much of its time waiting while
instructions and data are being fetched from the main memory.
– Major obstacle towards achieving good performance.

• Speed of the main memory cannot be increased beyond a

certain point.
• Cache memory is an architectural arrangement which makes
the main memory appear faster to the processor than it really
is.
• Cache memory is based on the property of computer
programs known as “locality of reference”.
 Locality of Reference
• Analysis of programs indicates that many instructions in
localized areas of a program are executed repeatedly during
some period of time, while the others are accessed relatively
less frequently.
– These instructions may be the ones in a loop, nested loop or few procedures
calling each other repeatedly.
– This is called “locality of reference”.
• Temporal locality of reference:
– Recently executed instruction is likely to be executed again very soon.
• Spatial locality of reference:
– Instructions with addresses close to a recently instruction are likely
to be executed soon.
 Cache memories

Process Main
Cache memory
or

• Processor issues a Read request, a block of words is transferred from the

main memory to the cache, one word at a time.
• Subsequent references to the data in this block of words are found in the
cache.
• At any given time, only some blocks in the main memory are held in the
cache. Which blocks in the main memory are in the cache is determined
by a “mapping function”.
• When the cache is full, and a block of words needs to be transferred
from the main memory, some block of words in the cache must be
replaced. This is determined by a “replacement algorithm”.
 Mapping functions
Mapping functions determine how memory
blocks are placed in the cache.
A simple processor example:
 Cache consisting of 128 blocks of 16 words each.
 Total size of cache is 2048 (2K) words.
 Main memory is addressable by a 16-bit address.
 Main memory has 64K words.
 Main memory has 4K blocks of 16 words each.
Three mapping functions:
 Direct mapping
 Associative mapping
 Set-associative mapping.
 Direct mapping
• Block j of the main memory maps to j modulo 128
Main Block 0 of the cache. 0 maps to 0, 129 maps to 1.
memory
• More than one memory block is mapped onto the
Cache Block 1
tag
same position in the cache.
Block 0 • May lead to contention for cache blocks even if
tag
Block 1 the cache is not full.
Block 127 • Resolve the contention by allowing new block to
replace the old block, leading to a trivial
Block 128
replacement algorithm.
tag
Block 127 Block 129

• Memory address is divided into three fields:

• - Low order 4 bits determine one of the 16
Block 255
words in a block.
Tag Block Word • - When a new block is brought into the cache,
Block 256
5 7 4
the next 7 bits determine which cache block this
Main memory address Block 257 new block is placed in.
• - High order 5 bits determine which of the
possible 32 blocks is currently present in the
cache. These are tag bits.
Block 4095 • Simple to implement but not very flexible.
 Associative mapping
• Main memory block can be placed into any
Main Block 0
memory cache position.
Cache Block 1 • Memory address is divided into two fields:
tag
Block 0
• - Low order 4 bits identify the word within
tag
Block 1 a block.
Block 127 • - High order 12 bits or tag bits identify a
Block 128 memory block when it is resident in the
tag
Block 127 Block 129
cache.
• Flexible, and uses cache space efficiently.
• Replacement algorithms can be used to
replace an existing block in the cache when
Tag Word
Block 255 the cache is full.
12 4 Block 256 • Cost is higher than direct-mapped cache
Main memory address Block 257 because of the need to search all 128
patterns to determine whether a given block
is in the cache.
Block 4095
 Set-Associative mapping
• Blocks of cache are grouped into sets.
• Mapping function allows a block of the main
Cache
Main Block 0 memory to reside in any block of a specific set.
memory
tag Block 0 • Divide the cache into 64 sets, with two blocks per
Block 1
tag
set.
Block 1
• Memory block 0, 64, 128 etc. map to block 0, and
tag Block 2 they can occupy either of the two positions.
tag Block 3 • Memory address is divided into three fields:
Block 63
• - 6 bit field determines the set number.
Block 64 • - High order 6 bit fields are compared to the tag
tag
Block 126 Block 65 • fields of the two blocks in a set.
tag • Set-associative mapping combination of direct and
Block 127
• associative mapping.
• Number of blocks per set is a design parameter.
Tag Block Word
Block 127 • - One extreme is to have all the blocks in one set,
6 6 4 Block 128 • requiring no set bits (fully associative mapping).
Block 129
• - Other extreme is to have one block per set, is
Main memory address
• the same as direct mapping.

Block 4095
 Cache hit
• Existence of a cache is transparent to the processor. The processor issues
Read and Write requests in the same manner.
• If the data is in the cache it is called a Read or Write hit.
• Read hit:
 The data is obtained from the cache.
• Write hit:
 Cache has a replica of the contents of the main memory.
 Contents of the cache and the main memory may be updated simultaneously.
This is the write-through protocol.
 Update the contents of the cache, and mark it as updated by setting a bit
known as the dirty bit or modified bit. The contents of the main memory
are updated when this block is replaced. This is write-back or copy-back
protocol.
 Cache miss
• If the data is not present in the cache, then a Read miss or Write miss occurs.
• Read miss:
 Block of words containing this requested word is transferred from the memory.
 After the block is transferred, the desired word is forwarded to the processor.
 The desired word may also be forwarded to the processor as soon as it is transferred
without waiting for the entire block to be transferred. This is called load-through or
early-restart.
• Write-miss:
 Write-through protocol is used, then the contents of the main memory are
updated directly.
 If write-back protocol is used, the block containing the
addressed word is first brought into the cache. The desired word
is overwritten with new information.
 Cache Coherence Problem
• A bit called as “valid bit” is provided for each block.
• If the block contains valid data, then the bit is set to 1, else it is 0.
• Valid bits are set to 0, when the power is just turned on.
• When a block is loaded into the cache for the first time, the valid bit is set to 1.
• Data transfers between main memory and disk occur directly bypassing the cache.
• When the data on a disk changes, the main memory block is also updated.
• However, if the data is also resident in the cache, then the valid bit is set to 0.
• What happens if the data in the disk and main memory changes and the write-
back protocol is being used?
• In this case, the data in the cache may also have changed and is indicated by the
dirty bit.
• The copies of the data in the cache, and the main memory are different. This is
called the cache coherence problem.
• One option is to force a write-back before the main memory is updated from the
disk.
The Memory System

Virtual Memory
 Virtual memories
 Recall that an important challenge in the design
of a computer system is to provide a large, fast
memory system at an affordable cost.
 Architectural solutions to increase the effective
speed and size of the memory system.
 Cache memories were developed to increase the
effective speed of the memory system.
 Virtual memory is an architectural solution to
increase the effective size of the memory system.

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 Virtual memories (contd..)
 Recall that the addressable memory space depends on
the number of address bits in a computer.
 For example, if a computer issues 32-bit addresses, the addressable memory space is 4G
bytes.
 Physical main memory in a computer is generally not
as large as the entire possible addressable space.
 Physical memory typically ranges from a few hundred megabytes to 1G bytes.
 Large programs that cannot fit completely into the
main memory have their parts stored on secondary
storage devices such as magnetic disks.
 Pieces of programs must be transferred to the main memory from secondary storage before
they can be executed.

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 Virtual memories (contd..)
When a new piece of a program is to be
transferred to the main memory, and the
main memory is full, then some other piece in
the main memory must be replaced.
 Recall this is very similar to what we studied in case of cache memories.
Operating system automatically transfers data
between the main memory and secondary
storage.
 Application programmer need not be concerned with this transfer.
 Also, application programmer does not need to be aware of the limitations
imposed by the available physical memory.

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 Virtual memories (contd..)
 Techniques that automatically move program and data between
main memory and secondary storage when they are required
for execution are called virtual-memory techniques.
 Programs and processors reference an instruction or data
independent of the size of the main memory.
 Processor issues binary addresses for instructions and data.
 These binary addresses are called logical or virtual addresses.
 Virtual addresses are translated into physical addresses by a
combination of hardware and software subsystems.
 If virtual address refers to a part of the program that is currently in the main memory,
it is accessed immediately.
 If the address refers to a part of the program that is not currently in the main
memory, it is first transferred to the main memory before it can be used.

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 Virtual memory organization
Processor
•Memory management unit (MMU)
translates virtual addresses into physical
Virtual address
addresses.
•If the desired data or instructions are in the
Data MMU
main memory they are fetched as described
previously.
Physical address •If the desired data or instructions are not in
the main memory, they must be transferred
Cache from secondary storage to the main memory.
•MMU causes the operating system to bring
Data Physical address the data from the secondary storage into the
main memory.
Main memory

DMA transfer

Disk storage

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 Address translation
 Assume that program and data are composed of
fixed-length units called pages.
 A page consists of a block of words that occupy
contiguous locations in the main memory.
 Page is a basic unit of information that is
transferred between secondary storage and main
memory.
 Size of a page commonly ranges from 2K to 16K
bytes.
 Pages should not be too small, because the access time of a secondary storage
device is much larger than the main memory.
 Pages should not be too large, else a large portion of the page may not be used,
and it will occupy valuable space in the main memory.

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 Address translation (contd..)
• Concepts of virtual memory are similar to the
concepts of cache memory.
• Cache memory:
– Introduced to bridge the speed gap between the processor and the main
memory.
– Implemented in hardware.

• Virtual memory:
– Introduced to bridge the speed gap between the main memory and secondary
storage.
– Implemented in part by software.

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 Address translation (contd..)
 Each virtual or logical address generated by a
processor is interpreted as a virtual page number
(high-order bits) plus an offset (low-order bits) that
specifies the location of a particular byte within that
page.
 Information about the main memory location of each
page is kept in the page table.
 Main memory address where the page is stored.
 Current status of the page.
 Area of the main memory that can hold a page is
called as page frame.
 Starting address of the page table is kept in a page
table base register.

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 Address translation (contd..)
• Virtual page number generated by the
processor is added to the contents of the page
table base register.
– This provides the address of the corresponding entry in the page table.

• The contents of this location in the page table

give the starting address of the page if the
page is currently in the main memory.

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 Address translation (contd..)
PTBR holds Virtual address from processor
Page table base register
the address of
the page table. Page table address Virtual page number Offset
Virtual address is
interpreted as page
+ number and offset.
PAGE TABLE
PTBR + virtual
page number provide
the entry of the page This entry has the starting location
in the page table. of the page.

Page table holds information

about each page. This includes
the starting address of the page
in the main memory. Control
bits
Page frame
in memory Page frame Offset

Physical address in main memory

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 Address translation (contd..)
 Page table entry for a page also includes some
control bits which describe the status of the page
while it is in the main memory.
 One bit indicates the validity of the page.
 Indicates whether the page is actually loaded into the main memory.
 Allows the operating system to invalidate the page without actually removing it.
 One bit indicates whether the page has been
modified during its residency in the main
memory.
 This bit determines whether the page should be written back to the disk when it is
removed from the main memory.
 Similar to the dirty or modified bit in case of cache memory.

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 Address translation (contd..)
• Other control bits for various other types of
restrictions that may be imposed.
– For example, a program may only have read permission for a page, but not
write or modify permissions.

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 Address translation (contd..)
 Where should the page table be located?
 Recall that the page table is used by the MMU for
every read and write access to the memory.
 Ideal location for the page table is within the MMU.
 Page table is quite large.
 MMU is implemented as part of the processor chip.
 Impossible to include a complete page table on the
chip.
 Page table is kept in the main memory.
 A copy of a small portion of the page table can be
accommodated within the MMU.
 Portion consists of page table entries that correspond to the most recently accessed pages.

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 Address translation (contd..)
 A small cache called as Translation Lookaside
Buffer (TLB) is included in the MMU.
 TLB holds page table entries of the most recently accessed pages.
 Recall that cache memory holds most recently
accessed blocks from the main memory.
 Operation of the TLB and page table in the main memory is similar to the
operation of the cache and main memory.
 Page table entry for a page includes:
 Address of the page frame where the page resides in the main memory.
 Some control bits.
 In addition to the above for each page, TLB must
hold the virtual page number for each page.

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 Address translation (contd..)
Virtual address from processor

Virtual page number Offset Associative-mapped TLB

High-order bits of the virtual address
generated by the processor select the
TLB
virtual page.
Virtual page Control Page frame
number bits in memory These bits are compared to the virtual
page numbers in the TLB.
If there is a match, a hit occurs and
the corresponding address of the page
No frame is read.
=?
If there is no match, a miss occurs
Yes
and the page table within the main
Miss
memory must be consulted.
Hit Set-associative mapped TLBs are
found in commercial processors.
Page frame Offset

Physical address in main memory

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 Address translation (contd..)
 How to keep the entries of the TLB coherent with
the contents of the page table in the main
memory?
 Operating system may change the contents of
the page table in the main memory.
 Simultaneously it must also invalidate the corresponding entries in the TLB.
 A control bit is provided in the TLB to invalidate
an entry.
 If an entry is invalidated, then the TLB gets the
information for that entry from the page table.
 Follows the same process that it would follow if the entry is not found in the TLB or
if a “miss” occurs.

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 Address translation (contd..)
What happens if a program generates an
access to a page that is not in the main
memory?
In this case, a page fault is said to occur.
 Whole page must be brought into the main memory from the disk, before
the execution can proceed.
Upon detecting a page fault by the MMU,
following actions occur:
 MMU asks the operating system to intervene by raising an exception.
 Processing of the active task which caused the page fault is interrupted.
 Control is transferred to the operating system.
 Operating system copies the requested page from secondary storage to
the main memory.
 Once the page is copied, control is returned to the task which was
interrupted.

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 Address translation (contd..)
• Servicing of a page fault requires transferring
the requested page from secondary storage to
the main memory.
• This transfer may incur a long delay.
• While the page is being transferred the
operating system may:
– Suspend the execution of the task that caused the page fault.
– Begin execution of another task whose pages are in the main memory.

• Enables efficient use of the processor.

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