Technical Presentation on Riviera Pro

Palash Gupta
Application Engineer
 Significance Of Design Verification
 Detecting and fixing design flaws

 Meeting functional requirements

 Ensuring compatibility and integration

 Mitigating risks and reducing costs

 Meeting industry standards and compliance

 Improving time-to-market

 Enhancing product quality and reliability

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 Challenges and Pain Points
 Increasing design complexity

 Time-to-market pressure

 Scalability and capacity limitations

 Functional coverage closure

 Verification methodology selection

 Design-for-Verification (DFV) complexity

 Integration and compatibility issues

 Debugging and error tracing

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 Aldec Overview
• Provider of state-of-the-art design/verification
tools for SoC, FPGAs/ASICs
• Founded 1984
• Privately Held, Profitable
• Over 35,000 + active user community
• 50+ global partners
• Aldec Solutions
 FPGA DESIGN
 FUNCTIONAL VERIFICATION
 EMULATION/ACCELERATION
 EMBEDDED SOLUTIONS
 ASIC/SOC PROTOTYPING
 HIGH PERFORMANCE COMPUTING
 MIL/AERO SOLUTIONS
• Key Technology Patents

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 Aldec Partnerships
Unite Partners

Unite IP Partners

Training Partners

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Aldec Customers (Software-based Solutions)

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Aldec Customers (Hardware-based Solutions)

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 Technology Focus
Design Creation
Verification
Hardware Validation
Niche Solution

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 Aldec Products

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 Riviera-Pro

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 Riviera-Pro

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 Riviera-Pro

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 Features

 Assertion-based verification
(ABV)
 Advanced simulation
performance
 Coverage-driven verification
(CDV)
 Debugging and analysis features
 Mixed-language and mixed-
signal support
 System-Verilog support
 Easy integration with other tools
and methodologies
 Extensive user community and
support

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 Riviera- Pro
Supported Standards
Design Entry and Design Management
-VHDL IEEE 1076 (1993, 2002, 2008
-HDL and Text Editor
and 2019)
-UVM Generator & Register Model
-Verilog® HDL IEEE 1364 (1995, 2001
Generator
and 2005)
-Auto-Complete and Code Templates
-SystemVerilog IEEE 1800 - 2012
-Automatic Code Analysis
(Design)
-Design Manager
-SystemC™ 2.3.1 IEEE 1666™/TLM 2.0
-Customizable GUI Perspectives and
-SystemVerilog IEEE 1800™ (2005,
favorites
2009 and 2012) - Verification
-Task Management
-Verification Libraries (OSVVM, UVVM,
-Macro, Tcl, Perl script support
cocotb)
-IP-XACT IEEE 1685 (2009 and 2014)
as a UVM register generator input
-Universal Verification Methodology

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 Riviera- Pro
Debug and Analysis Simulation/Verification

-Advanced Breakpoint Management -Single or Mixed Language

-Interactive Code Execution Tracing -Verilog Programming Language Interface (PLI/VPI)
-Accelerated Waveform Viewer (ASDB) for Riviera -VHDL Programming Language Interface (VHPI)
-Hierarchical References to/from VHDL (Signal -SystemVerilog IEEE 1800 DPI 2.0
Agent) -Value Change Dump (VCD and Extended VCD) Support
-Post Simulation Debug -Incremental Compilation
-Multiple Waveform Windows -Multi-Threaded Compilation
-Waveform Comparison, Memory Viewer -Simulation Model Protection
-Plot Window, Image Viewer -IEEE 1735™ Interoperable Encryption
-FSM debug, Classes Window -VHDL IEEE 1076™-2008 Encryption
-Integrated Source Level C/SystemC Debugger -Verilog® IEEE 1364™-2005 Encryption
-Assertions Debugging -Xilinx® ISE SecureIP Support
-Synopsys® (formerly SpringSoft) Verdi™ FSDB -64-Bit Simulation
Interface -Simulation Performance Optimization (Verilog/SV, VHDL)
-X-Trace -Dynamic Object Tracing
-Dataflow, UVM Graph & Toolbox -Transaction-Level Visual Debugging
-Profiler (Performance Metrics)
-SFM (Server Farm Manager)
-Hardware Assisted Verification
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 Riviera- Pro
Assertions and Coverage Tools Licensing

-Code Coverage(Statement, Branch, Expression, -Floating License

Condition, Path, FSM), Toggle Coverage, -One Year Time Based License
and Functional Coverage (OSVVM) + New UCIS- -Perpetual License
compatible Aldec Coverage Database
-PSL IEEE 1850, SystemVerilog IEEE 1800™
-Functional Coverage (Covergroup) Supported Platforms

Co-Simulation Interfaces -Linux® (64-Bit)

-Windows® 11/10/Server 2022, 2019, 2016, 2012 (64-Bit)
-Keysight SystemVue® (formerly Agilent Test and
Measurement)
-MathWorks Simulink®
-MathWorks MATLAB®
-Aldec QEMU Bridge (Linux Only)

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 AMD® Versal™ ACAP Designs

 Riviera-PRO Supports System Simulation of

AMD® Versal™ ACAP Designs
 AI Engine (AIE), Processing System (PS),
Programmable Logic (PL), Network on Chip
(NoC) and hardened domain-specific IPs such as
PCIe Gen5 with DMA and CCIX, HBM, 600G
Interlaken and 600G Ethernet.
 Enables heterogeneous computing
 SystemC models are also available for the AIE
and NoC

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 Create with Riviera-PRO

Advanced technology behind a

Analyze Create simple user interface:
• Effective • Intuitive best-
debug in-class GUI  Flexible design
management
environment  Multi-threaded framework
 Customizable perspectives
 Featured HDL Editor
Simulate  Design Rule Checking

• Industry-leading
performance

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 Design Management
› Design Manager facilitates management of workspaces and designs:
› Adding/removing/activation of designs
› Adding/removing/opening sources
› Compilation of files and designs
› Selection of config. (debug/release)

› User selects location of design files:

› Design Manager shows files picked as
design items

› All files, even those not displayed

as design items, can be accessed
via Filesystem

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 Library Management
› Libraries window allows performing various
operations on libraries:
› View and manipulate library contents
› Create and delete libraries
› Create and delete library mappings and links
› Initialize simulation

› Enables operations on local and global

libraries
› Local libraries are workspace/design specific
› Global libraries are used by all designs

› Contents of each library can be viewed after

expanding library branch in the library tree

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 Customizable Perspectives
› Five predefined perspectives for quick change of GUI layout while
switching between different tasks:
› Default – ideal for basic design management and quick simulation
(Design and Library Managers, Documents and Console)
› Debug – shows debugging tools for detailed analysis of simulation
(Breakpoint editors, Watch, Call Stack, Assertion/Cover viewers, etc.)
› Coverage – activating this perspective opens windows
helpful while analyzing coverage results
› Console – maximizes the Console to facilitate analysis of
simulation messages
› Documents – removes all windows but Documents;

› Note: custom (user-defined) perspectives can be created

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 Favorite
s › Pin your favorites
scripts, executables or
viewers, wherever you
want

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 HDL Editor
› Support of all standard file types:
› VHDL, Verilog/SystemVerilog
› SystemC, C/C++
› SVA, OVA, PSL
› EDIF, SDF, Tcl/Tk, .do Macro
› Enhanced code visualization:
› Syntax highlighting
› Structure generation
› Back-annotation
› Auto-formatting
› Block editing
› Auto-complete, Code Templates
› Bookmarks
› Enhanced printing options
› Automatic Code Analysis

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 Outline
› Outline window is a tool that displays
elements of source code while a source
file is edited in the HDL Editor and before
it is compiled to a working library

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 Project Tasks Management
› The Tasks window enables managing tasks scheduled to do in a project;
the tasks can come from:
› Source code analysis (predefined TODO and FIXME tags)
› User-defined items in the Tasks window

Tagged comments…

…are auto-recognized

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 Testbench Creation

› Stimulus Editor defines stimuli for signals,

similarly to the force command:
› Available stimulus types include:
Clock, Counter, Formula, Random,
Custom, and Text
› Stimuli defined in the editor
can be saved to a macro

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 FSM Coverage

› Allows to identify not visited states

and sequences of states
› Allows to identify not evaluated
transitions
› SystemVerilog IEEE Std 1800™-2012
pragmas support
› Aldec's proprietary extensions
pragmas for SystemVerilog and VHDL

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 UVM Generator
› UVM Generator is a tool that helps
starting a new UVM design.

› The tool generates a set of

SystemVerilog and Tcl files that are the
framework of a UVM design.

› The generated code can be

used as a starting point to develop it
further to create the UVM verification
testbench.

› This approach can make adopting of

UVM easier for the newcomers.
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 UVM Register Generator
› Register Generator (RAL) allows the user to generate the RTL
register model , UVM register model with coverage, documentation
and header files for C applications automatically.

› Models can be generated from the IP component description in IP-

XACT format or Aldec's format utilizing CSV spreadsheets.

› The register_generator program can generate the register

model in the following output formats :
› UVM Register Model with coverage
› RTL Register Model in VHDL/Verilog
› C Header
› HTML

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 UVM Registers Window

› The UVM Registers window has

been introduced.

› The window presents the register

models available in the design and
lists their properties.

› The register model can be viewed

as a hierarchy of register blocks or
as a memory map.

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 Simulate with Riviera-PRO

 High performance kernel

Analyze Create
 All standard languages
• Effective • Intuitive best-
 All platforms, 32/64 bit
debug in-the-class
environmen GUI  External interfaces
t  Hardware emulation & acceleration
 Regression testing automation

Simulate
• Industry-
leading
performance

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 Languages and Platforms

› Common kernel with comprehensive support of all the

standard languages:
› VHDL, Verilog/SystemVerilog, SystemC, C/C++
› Behavioral, RTL, gate-level and timing (SDF) simulation

› Available on the following platforms:

› Windows® 11, 10, Server 2022,2019,2016,2012 64 bit
› Linux x86_64

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 Verification Libraries
› Universal Verification Methodology (UVM) is a standard to enable
guaranteed development and reuse of verification environments and
verification IP (VIP) throughout the electronics industry.
› The latest UVM library is supported (UVM 1800.2-2017)
› Expanded transaction visualization capabilities
› Scripting shortcuts

Examples Library

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 High Performance Simulation Kernel

› Compilation and simulation optimization algorithms:

› Extensive simulation optimization algorithms to achieve the highest
performance in VHDL, Verilog/SystemVerilog, SystemC, and mixed-
language simulations
› The industry-leading capacity and simulation performance enable high
regression throughput for developing the most complex systems
› Multi-threaded VHDL and Verilog/SV compilation

› Effective library management:

› Incremental compilation
(skip design units that were not modified
since the previous session)

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 Advanced Scripting with Tcl

› Native support for the Tcl, the industry-standard

scripting and automation language:
› Controlling macro execution flow
› Handling breakpoints and errors
› Redirecting output
› Running OS commands
› Accessing environment variables
› Creating custom commands

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 IP Encryption

› Support for the latest industry standards:

› IEEE 1735 Version 1 Recommendations
› Encryption methods defined in Verilog
IEEE Std 1364-2005 and VHDL IEEE 1076-2008 Standards
› Simulating encrypted files requires no action at Riviera-PRO user’s side
(given IP vendor encrypted the files for target simulation tool)
› Decrypts the source on-the-fly, leaving no traces that could compromise the
security of encryption
› Supports DES, 3DES, AES and Blowfish encryption algorithms
› Up to 256 bit encryption keys (AES)

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 Simulation Interfaces

›Flexible API, PLI/VPI/VHPI, and DPI-

C/DPI-SC support:
› Synopsys® SWIFT Models
› Denali Memory models
› Synopsys® (ex-SpringSoft®)
Debussy/Verdi™ Interface (FSDB)
› Direct interface to compiled SystemC
code (native SystemC interface),
bypassing the cumbersome and slow
PLI/VHPI interfaces in mixed
Verilog/VHDL/SystemC simulations
› All other IEEE compliant interfaces

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MATLAB® Co-Simulation Interface
› Riviera-PRO provides bidirectional MATLAB/Simulink/HDL Coder
co-simulation interface, enabling engineers to:
› Verify that their ASIC/FPGA implementations match system specs
› Perform system-level hardware verification

HDL HDL

𝑦= Co-Sim. Interface
𝑓𝑓(𝑥)
HDL HDL

› Hardware defined in HDL can be tested with a DSP algorithm or incorporated

into a Simulink design
› Note: MathWorks MATLAB/Simulink software license is required to use the
co-simulation interface

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 OpenCPI Support

› Open Component Portability Infrastructure (OpenCPI) is an open source

software (OSS) framework for developing and executing component-based
applications on heterogeneous embedded systems

› OpenCPI supports defining, implementing, building and testing components,

as well as executing applications based on those components in the targeted
embedded systems

› OpenCPI also helps with code portability and reusability by providing the APIs,
software modules and IP cores that abstract the complexities of the underlying
hardware platform

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QEMU Interface – Aldec QEMU Bridge

› Aldec QEMU Bridge assures:

› Full debug capabilities of RTL IP Core in
Riviera-PRO simulator:
› Waveforms
› Hardware Breakpoints
› Hardware steps
› Kernel and driver debug via GDB
› Software Breakpoints
› Variable probing
› Zynq Linux OS ready to use on QEMU without
modifications

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QEMU Interface – Aldec QEMU Bridge

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 Emulation & Acceleration Integration
(The Verification Spectrum option)

› Aldec HES-DVM™
› Acceleration – speedup
verification process
x10—100 times using
integrated HW/SW
co-simulation solution
› Emulation – verify your design
in real hardware using the
TLM testbench with SCE-MI
interface

› Aldec HES
› FPGA-based ASIC prototyping
› Scalable up to 633 million

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 Regression Test Automation
(The Verification Spectrum option)

› Aldec SFM™
› Server Farm Manager + Riviera-PRO =
complete solution for regression testing
› 32/64-bit platform support
› Remote administration through the web-
interface:
› Set-up, Execution and Data Analysis
› Compare test results across design versions
› Revision history, regressions and bug tracking
› Quick Test Scenarios
› Predefined scripts for typical EDA tools

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 Analyze with Riviera-PRO

 Integrated debugging environment

Analyze Create
 Dataflow visualization
• Effective • Intuitive best-
 Post-simulation debug
debug in-the-class
environmen GUI  Fast waveform viewer
t  Coverage viewers – metric-driven verification
 Design Rule Checking

Simulate
• Industry-
leading
performance

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 Dataset Management

› Simulation data is saved into an ASDB

dataset – a combination of hierarchy
database and simulation database
› Datasets window allows attaching multiple
datasets (waveform comparison,
post-simulation debugging)
› Hierarchy window shows structure of the
simulated model and helps selecting contents
of the debugging windows
› Objects window shows objects inside the
design unit selected in Hierarchy
Viewer

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 Advanced Waveform Viewer

› Presents data from one or more simulation databases:

› Displays signal/variable values and status of assertion/cover statements,
simulation messages, transactions, and classes
› Multiple cursors, bookmarks, extensive search and browsing features
› Shows delta cycle expansion and analog display of buses

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 Breakpoint Management

› The following breakpoint editors are available:

› Signal
› HDL Code
› C Code
› Assertion
› Cover

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 Watch Window

› Watch window displays values of selected objects (signals,

variables, nets, registers, assertions, covers ) in the simulated
model.

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 Subprogram Tracing

› The Locals window displays arguments of the currently executing

subprogram and objects/variables defined within that subprogram;
› VHDL procedures and functions, Verilog automatic tasks and automatic
functions, and C/C++ functions.
› The Call Stack shows a call stack of HDL subprograms or a call stack of C/C++
function calls.

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 Signal Drivers and Readers

› Drivers and Readers window displays processes driving a given signal

(drivers) and processes driven by that signal (readers)

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 Contributors

› One-click waveform tracing for contributors

› Contributing signals, called contributors, are specified as the
input signals to the process driving the given signal

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 Dataflow Visualization

› The Dataflow window enables:

› Graphical exploration of hierarchical blocks, processes and signals
› Investigation of errors reported during post-synthesis/timing simulation

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 Cause Finder

› The Cause Finder window is a tool that displays a graph presenting

possible sources of X values in a design. The tool displays object
values starting from the one with X value and goes back in time to
the first driver that caused this value

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 FSM Window

› FSM window displays the color-coded graph that shows state transition

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 Memory Viewer

› Provides flexible, user-configurable display of contents of various

memory structures:
› Cell contents modification
› Memory save and load (.hex and .mif)
› SV dynamic arrays and queues display

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 Transaction-Level Debugging

› Record transactions into an .asdb file during simulation

› Analyze transactions and their attributes in the Waveform and
Transaction Data window
› Use post-simulation debug as necessary

TLM Wavefor
Simulator
Testbench m File
(.asdb)

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 Classes Window

› The Classes window presents SystemVerilog classes in the form of a

hierarchical tree view:
› The view includes class inheritance and displays the list of methods and
properties
declared within the class.

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 SystemVerilog Classes in Waveform

› The wave and log commands can trace dynamic objects

(classes), enabling analysis over time:
› A class object is presented as a handle which holds the references to the
instance(s) of this class; the references are presented as @n
mnemonics

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 UVM Graph

› UVM Graph presents UVM testbench architecture, UVM

components, objects and the transaction level modeling (TLM)
connections
Agent

Sequencer

Driver Monitor

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 UVM Toolbox

› UVM Hierarchy presents

the hierarchy of the UVM
components and displays their
properties

› UVM Configuration
window presents the resources
available in the UVM
configuration database during
interactive debugging session

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 Assertion and Cover Viewers
› The Assertions and Covers windows show:
› PSL, SVA, and OVA assertions and cover statements bound to the design
› Assertion/cover names, signals used in each assertion, assertion state,
assertion execution counts, etc.

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 Code and Functional Coverage Viewers
› Dedicated tools and .html reports that display coverage data
gathered during simulation:
› Code Coverage (Statement, Branch,
Expression/Condition, FSM, Toggle, Path)
› Functional (Assertion, Covergroup)
Coverage

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 Code and Functional Coverage Viewers

› Code Coverage results are presented directly in the HDL Editor

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 Covergroup Viewer

› Complex functional coverage presented in transparent way

› The window displays declarations, instances, and components

of covergroups available in the design and shows the number
of hits and coverage goals associated with these objects.
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 FSM Coverage Viewer
› FSM coverage presented as a graph with transition table

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 FSM Debugging

› FSM table and FSM Attributes window allows to seek for time, values
and transitions between selected states
› FSM List window provides detailed information about coverage of all
FSM’s in the design

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 Verification Plan

› Enables validating the

verification process with a
test plan
› It allows users to link
the requirements from test
plan to coverage results to
see if verification goals have
been reached or not
› Allows user to rank
tests to select minimal
testsuit for regression
Verification flow with a user-defined test plan
tests

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 Alias Management

› Aliases window enables creating convenient, easy to recognize names

and color attributes for values of certain objects:
› Other debugging windows can display aliases instead of plain values
› Mnemonics can be displayed for complete objects or their slices (use Slices window
to define them)

› Note: when view of the object does not allow readable display of alias mnemonic
(due to zoom-out condition), distinctive color is still visible.

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 Built-in Console

› Console is the basic input-output:

› Advanced transcript area:
› Cross-probing to other GUI
tools (e.g. to HDL
Editor)
› Tabs (filtered views)
› Drag-and-drop
operations from other
debug windows
› Command prompt with
autocomplete feature
› Filter toolbar enables filtering
by message severity, arbitrary
strings, or message sources

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Plot-Based Data Visualization

› Plot & Image windows enable a visual analysis of HDL objects:

› functions or relations among variables
› values of objects as a function of other variables
(vs. Waveform that only displays object values as a function of time)

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 Histogra
m › Histogram from Object or File ( View->Debug->Histogram )

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 RTL Design Rule Checking
(Aldec ALINT-PRO - The Verification Spectrum option)
› Detects wide variety of design
problems at design entry
› Be aware of hidden bugs
(from synthesizability to CDC and
DFT issues)
› Prevent issues at subsequent stages
of the flow (avoid costly re-spins)
› Get started quickly using predefined
design checking policies
› Pick a dedicated rule plug-in
(STARC, DO-254, RMM, CDC)
› Use GUI pplication for efficient analysis
of rule violations

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 Testimonials

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 Summary
› Comprehensive verification environment for SoC/ASIC/FPGA
› Industry-leading simulation performance and capacity
› Linux and Windows 64-bit OS support
› Comprehensive support of standard languages
› Integration with other products (Aldec and other vendors)
› Comprehensive integrated debugging and linting environment
› Complete coverage support for metric-driven verification
› Comprehensive support for OVM, UVM, OSVVM, UVVM
› SW/HW Co-simulation

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 Active-HDL™
FPGA DESIGN CREATION
AND SIMULATION
Windows® based, integrated FPGA Design Creation
and Simulation solution for team-based environments.

› IEEE VHDL, Verilog, SystemVerilog (Design)

› Team-based design Management
› Mixed Language Simulation and Debugging
› Multi-FPGA & EDA Tool Design Flow Manager
› HTML and PDF Design Documentation
› Graphical Design Entry & Editing
› FPGA Vendor Library Support
› Windows® 10/8.1/7/2012/2008/2003 32/64-bit

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 ALINT-PRO™
DESIGN RULE CHECKING &
CDC/RDC ANALYSIS
ALINT-PRO™ design analysis tool decreases verification
time dramatically by identifying critical issues early in the
design stage.
› Clock and Reset Networks Analysis
› Avoiding post RTL and post Synthesis Simulation Mismatches
› Verifying correctness of FSM descriptions
› Code Portability and Reuse
› Extensive CDC and RDC checks with ALDEC_CDC rule plug-in
› Advanced CDC and RDC Debugging Environment
› Schematic Viewer
› DFT Checks
› SDC™ Support
› Design Constraints Extension for IP Description
› Background and batch running modes

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 HES-
DVM™
HARDWARE EMULATION
SOLUTIONS
Fully automated and scalable hybrid verification
environment for SoC and ASIC designs, capable of
simulation acceleration, transaction level co-emulation,
virtual modeling, in-circuit emulation and prototyping.

› Scalable across FPGA technology with the of-the-shelf

HES boards and in-house made custom FPGA boards
› Based on standards: SCE-MI, TLM, SystemVerilog DPI-
C, VHDL, SystemC

› Superior debugging capabilities with automatic instrumentation, 100% visibility HVD technology and full
controllability
› Automated and scriptable design setup tool – DVM – supporting gated clocks and advanced partitioning
› VIP Library - Bus Models and Peripherals
› Supports Linux® and Windows®

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 HES™
SoC/ASIC PROTOTYPING
Provides SoC/ASIC hardware verification and software validation teams with a scalable and high quality FPGA-
based ASIC prototyping solution.
› Scalable up to 633 million ASIC gates
› Up to 6 FPGA on a single board and scaled to 24 on the
Backplane configuration
› Expandable with non-proprietary connectors
› Various peripherals and interfaces via daughter cards
including ARM® Cortex™ Support with Xilinx® Zynq™,
HDMI, USB, RF Wireless, Ethernet and more
› Allows sub-systems prototyping and complete SoC
integration
› Reuse for HES-DVM simulation acceleration and co-
emulation
› Superior Quality Backed by Industry Leading 1-Year
Warranty
› Trusted vendor with over 30 years of experience in
verification and FPGA prototyping

78 www.aldec.com Aldec Overview

 HES™
HIGH-PERFORMANCE
COMPUTING
Targets leading-edge algorithms and applications in the areas of
Computer Vision, Encryption & Security, Genome Alignment
and High Frequency Trading. Aldec’s solution consists of :
› Hardware - Re-configurable FPGA-based accelerator
board
› HES-7 or HES-US – FPGA based prototyping board
› PCI Express host link adapter
› Proto-AXI Interface IP
› Software
› HES.Asic.Proto
› HES PCI Express driver
› Proto-AXI software API
› Linux & Windows supported
› Reference designs and integrations services
› Quick integration services

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 TySOM
™HIGH PERFORMANCE EMBEDDED
DEVELOPMENT
Based on Xilinx Zynq 7000 or MPSoC (FPGA + Dual ARM®
Cortex™-A9) with various peripherals targeting embedded vision,
machine learning, IIoT, ADAS and robotics. The kit includes:

› TySOM boards (TySOM-1-7Z030 or TySOM-2-7Z045/7Z100 or TySOM-

2A-7Z030 or TySOM-3-ZU7)
› Various FMC daughter cards
› Professional reference designs
› Multiple Linux OS ports
› uSD card pre-loaded with Ubuntu
› Power supply, HDMI, LAN and UART cables
› Includes Xilinx Vivado or SDSoC, 1 year device locked license

80 www.aldec.com Aldec Overview

 RTAX/RTSX
PROTOTYPING MICROCHIP™
RAD-TOLERANT DEVICES
Aldec and Microchip have joined together, offering a new,
innovative, reprogrammable prototyping solution for
Microchip RTAX-S/SL, RTAX-DSP and RTSX-SU space-
fight system designs.
› Supported Microchip devices/capacities
› RTAX-S/SL up to 4000S
› RTAX-DSP
› RTSX-SU
› Automated Device Netlist Converter
› Memory Conversion
› Physical Design Constraint (PDC) file conversion

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 DO-254/CTS™
FPGA TEST SYSTEM
Fully customized test system that includes
hardware and software; for use in the avionics
industry to satisfy objectives of FAA
RTCA/DO-254
› At-speed testing in the target FPGA device
› Reuse testbench as test vectors for testing
› FPGA I/Os full visibility/controllability
› Multi-asynchronous clock domain support
› Supports serial high-speed interfaces such as
PCIe, ARINC 818, ARINC 664 and LVDS
› For use with AMD®, Intel® and Microchip®
devices
› Independent assessment of simulator,
synthesis and P&R tool
› Normal and abnormal testing with power
supply and clock deviation

82 www.aldec.com Aldec Overview

 Thank You
Palash Gupta
[email protected]