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Optimization Synthesis

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Nishanth Gowda
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445 views

Optimization Synthesis

Uploaded by

Nishanth Gowda
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Timing Optimization

Different options
• Path groups
• Datapath implementation
• Boundary optimization (remove unintentional preserve on module/subdesign)
• Multibit flops removal (check the fanout-if less)
• Map_to_mux (Genus)
• Incremental compile
• Full compile (experimental)
• Optimize_netlist (DC command)
• HEOC (Genus in final incremental compile)
• constraints
• MBIST grouping based on the PD feedback
• Allow to use LVT/SLVT cells based on PD feedback
• Floorplan feedback
• Design team feedback
• Physical synthesis
Command:

group_path

Group_path –name pathA –weight 10.0 –critical_range 3.0 –to [filter_col [all_register –edge_tri –data_pins] full_name=*A]

Group_path –name pathB –weight 10.0 –critical_range 3.0 –to [filter_col [all_register –edge_tri –data_pins] full_name=*B]

Group_path –name pathC –weight 10.0 –critical_range 3.0 –to [filter_col [all_register –edge_tri –data_pins] full_name=*C]

Group_path –name pathC_1 –weight 50.0 –critical_range 3.0 –to [filter_col [all_register –edge_tri –data_pins] full_name=*C/C1]

Group_path –name pathA_1 –weight 50.0 –critical_range 3.0 –to [filter_col [all_register –edge_tri –data_pins] full_name=*A/A1]
DesignWare

Elab: sequential cell- SEQGEN


combinational cell : GTECH
Datapath implementation
• Datapath Implementation:

When the design has extensive use of arithmetic and shift operators, the following command controls the strategies used to generate the
Datapath for these operators.

Command:

set_datapath_architecture_options
-optimize_for auto | area | speed | area,speed
-power_effort auto | off | medium | high
Set_db_smartgen_options
Boundary optimization
Map_to_mux
Map_to_mux
Area optimization
Different options
• Set_max_area
• Compile –area_effort high or –map_effort high
• Compile –auto_ungroup
• Enable Boundary optimization for subdesigns
• dc_shell set_boundary_optimization subdesign true
• Optimize_netlist
Set_max_area
• Keep realistic number as possible,
• Mostly usage use set_max_area = 0
• If it is tightly constrained like 0 , area optimizations will be performed, till the time, timing of the design starts degrading against its
constrained value
• As timing constraints have higher priority then area constraints, So it will try to optimize area till the timing starts worsening. Having area
constraint as 0 will increase run time if timing constraints is not much aggressive
Compile –area_effort high or –map_effort high
Auto_ungroup
• By default, DC Explorer automatically ungroups small design hierarchies in the first pass of the compile, and it ungroups hierarchies along
critical paths using delay-based auto-ungrouping strategy in the second pass of the compile
Boundary optimization
When you enable boundary optimization, DC Explorer propagates constants, unconnected pins, and complement information. In designs that
have many constants (VCC and GND) connected to the inputs of subdesigns, propagation can reduce area

To enable area reduction with boundary optimization disabled,


set the compile_optimize_unloaded_seq_logic_with_no_bound_opt variable to true to remove unconnected logics
•Removes unconnected registers across design hierarchies
Optimize_netlist
Optimize_netlist
Power optimization
Compile –power_effort high
• DC

setOptMode –powerEffort {low| medium | High} (genus)


Leakage power optimization
To enable leakage power optimization

Set_leakage_optimization true (DC)

To enable power optimization (genus)


set_db leakage_power_effort {none | low | medium | high | auto}
Dynamic power optimization
• To enable leakage power optimization.
• Design compiler aspect switching activity information, so use saif file

The tool optimizes dynamic power by shortening the net lengths of high-switching activity nets.
Because the dynamic power saving is based on the switching activity of the nets,
you need to annotate the switching activity by using the read_saif command

Read_saif <saif file>

• Set_dynamic_optimization true (DC)

• setOptMode –powerEffort {low| medium | High} (genus)

• set_db dynamic_power_effort {none | low | medium | high | auto} (genus)

• Check clock gating implementation

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