PART II

INTERFACING
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PART II
INTERFACING
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 IN THIS PART:
Chapter 5
 Introduction
 The 8255 PPI
 The 8259 PIC
 The 8251 USART
 Memory Interfacing

Extra: PC interfacing standards

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OUTLINE
 Introduction
 The 8255 PPI

 The 8259 PIC

 The 8251 USART

 Memory Interfacing

 Extra: PC interfacing standards

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INTRODUCTION
 Two methods of communicating external equipment:
 MEMORY MAPPED I/O
 ISOLATED (DIRECT) I/O

 Memory Mapped I/O:

 Interface devices are mapped directly on to the system address and data bus
 Port will be written to/read from in the same way as any other memory

location
 A decoder translates memory addresses to chip select signals

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INTRODUCTION
 Peripheral Interfacing Needed
 To design and implement an 8086 based microcomputer system
 For the microprocessor to interact with the external world

 Types of Programmable Peripheral Devices

 General Purpose
 Special Purpose
 Input/output ports

zProgrammable Interrupt Controller (PIC)

zProgrammable interval timer

zProgrammable communication interface

zProgrammable DMA interface

zMultipurpose programmable device.
 While some of the special purpose peripherals are:

zProgrammable CRT controller
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
zProgrammable floppy disk controller

zProgrammable keyboard and display interface.
INTRODUCTION
 E.g. connecting a port device using 74LS138:

Then, data can be read;

e.g MOV AL, 0000 ;READS FROM PORT 0
Proglem: part of the address space is used by I/O

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INTRODUCTION
 Direct I/O
 Separate address spaces are set out for I/O ports
 Uses 16-bit addressing (0000 – FFFF)
 Advantage: none of the memory space is used for ports
 Disadvantage: only specialized IN and OUT instructions can
be used to input or output data
 E.g: IN AL, DX ;DX: port address
OUT DX, AL

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 PROGRAMMABLE PERIPHERAL
INTERFACE (PPI 8255A)
 A general purpose programmable I/O device
 Used for parallel data transfer (simple/inter. I/O)
 Designed for use with Intel’s 8-bit , 16-bit and higher capability MPs as well
as most other MPs

 It has 24 Input/Output lines (pins) which can be grouped into three 8-bit
parallel ports:
 Port A (PA0-PA7)
 Port B (PB0-PB7)
 Port C (PC0-PC7)
 All of the ports can function independently either as input or output ports
 Achieved by programming the bits of an internal register of 8255 called control word
register

 It can be programmed in two modes:

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 Bit Set Reset (BSR): to set/reset bits of port C
 I/O Mode: Mode 0, Mode 1, Mode 2
 THE 8255 PROGRAMMABLE
PERIPHERAL INTERFACE (PPI)
 A general purpose programmable I/O device
 Used for parallel data transfer (simple/inter. I/O)

 Designed for use with Intel’s 8-bit , 16-bit and higher

capability MPs as well as most other MPs

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PPI 8255A
 Pin diagram:
 It is a 40 pin IC which is
used to I/P or O/P digital
signal
 Has 24 I/O lines in 3 groups:
ports A, B, C
 Connects peripheral devices
like printers, keyboards,
controllers, DACs, ADCs

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 THE 8255 PPI
PIN DIAGRAM
 It is a 40 pin IC which is used to
I/P or O/P digital signal

 Has 24 I/O lines in 3 groups:

ports A, B, C

 Connects peripheral devices like

printers, keyboards, controllers,
DACs, ADCs

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 THE 8255 PPI
SIGNAL DESCRIPTION
 PA7-PA0:
 These are eight port A lines that acts as either latched output or
buffered input lines depending upon the control word loaded into
the control word register.
 PC7-PC4 :
 Upper nibble of port C lines. They may act as either output latches
or input buffers lines.
 This port also can be used for generation of handshake lines in
mode 1 or mode 2.
 PC3-PC0 :
 These are the lower port C lines, other details are the same as PC7-
PC4 lines.
 PB0-PB7 : 13
 These are the eight port B lines which are used as latched output
lines or buffered input lines in the same way as port A.
 THE 8255 PPI
SIGNAL DESCRIPTION
 RD
 This is the input line driven by the microprocessor and should be low to
indicate read operation to 8255
 WR
 This is an input line driven by the microprocessor. A low on this line
indicates write operation
 CS
 This is a chip select line. If this line goes low, it enables the 8255 to
respond to RD and WR signals, otherwise RD and WR signal are
neglected
 D0-D7
 These are the data bus lines those carry data or control word to/from the
microprocessor
 RESET 14
 A logic high on this line clears the control word register of 8255. All ports
are set as input ports by default after reset
 THE 8255 PPI
SIGNAL DESCRIPTION
 A1-A0
 These are the address input lines and are driven by the
microprocessor.
 These address lines are used for addressing any one of the
four registers, i.e. three ports and a control word register as
given in table below.

A1 A0
Port A 0 0
Port B 0 1
Port C 1 0
Control Register 1 1
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PPI 8255A
 The connection to MP is thru:
 data bus D0 – D7
 Handshaking and address lines (RD’, WR’, A1, A0, RESET)

 There are four registers in the device:

 PORT A
 PORT B

 PORT C

 CONTROL REGISTER

 Ports A, B and C – link to the I/P lines, O/P lines (PA0-

PA7, PB0-PB7, PC0-PC7)
 A port register is selected using address lines A0 and A1
as:
 00 selects Port A 01 selects Port B
 10 selects Port C 11 selects Control register 16
PPI 8255A
 Ports A and B can be used as 8-bit I/P or O/P
 Port C:
 as 8-bit I/P or O/P
 As two 4-bit ports

 To produce handshake signals for ports A and B

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PPI 8255A – BLOCK DIAGRAM

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 THE 8255 PPI
BLOCK DIAGRAM

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 THE 8255 PPI
BLOCK DIAGRAM…
 Data Bus Buffer
 Tri-state bi-directional buffer used to interface the 8255 to system
data bus
 Execution of I/O instructions by the CPU, either RD data from or
WR to into this buffer
 O/P data from CPU to ports or Control Register and I/P data to CPU
from ports or status register all passed through the buffer

 Control Logic
 Accepts control signals (RD, WR) and inputs from address bus
 Issues commands to individual group of control blocks (Group A and B)
 Issues appropriate enabling signals to access required data/control words or

status word

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 THE 8255 PPI
BLOCK DIAGRAM…
 Group A and Group B Controls
 Theseblocks receive control from the CPU and issues
commands to their respective ports
 Group A - PA and PCU (PC7 –PC4)
 Group B - PCL (PC3 – PC0)

 Control word register can only be written into no read

operation of the CW register is allowed
 Ports A and B
 Can be used as 8-bit I/P or O/P
 Port C:
 As 8-bit I/P or O/P
 As two 4-bit ports
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 To produce handshake signals for ports A and B
 PPI 8255A - MODES
 BSR Mode:
 Individual bits of port C can be set/reset by sending OUT instruction
to control register
 Do of the control word
 Determines whether the bits are to be set or reset
 D3, D2 and D1 of the control word
 Determines the particular bit to be set or reset
 Used to set/reset individual bits of port C when it is used for
control/status operation

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 PPI 8255A - MODES
 BSR Mode:
 Individual bits of port C can be set/reset by sending OUT instruction
to control register
 Do of the control word
 Determines whether the bits are to be set or reset
 D3, D2 and D1 of the control word
 Determines the particular bit to be set or reset
 Used to set/reset individual bits of port C when it is used for
control/status operation

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 PPI 8255A - MODES
 I/O modes:
 Mode 0 (Basic I/O )
 Mode 1 (Strobed I/O)
 Mode 2 (Bidirectional Strobed I/O)

 Port A can be programmed in 3 modes: Mode 0, Mode 1,

Mode 2
 Port B – Mode 0 and Mode 1
 Port C – as control signals for ports A and B in handshake
mode, or programmed for bit set/reset
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 PPI 8255A
MODE 0
 Ports A and B are used (& programmed) as two simple 8-
bit I/O ports, port C as two 4-bit ports (port C upper and
lower)
 Any port can be used as an input or output port

 The two 4-bit ports can be used together as a third 8-bit

port
 Input ports are not latched

 Output ports are latched

 Ports do not have the capability of handshake mode or

interrupt mode
 A maximum of four ports are available so that overall 16 25

I/O configuration are possible

PPI 8255A
MODE 0…

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PPI 8255A - MODES
 Mode 0: simple I/O
 Ports A and B are used (& programmed) as two simple 8-bit I/O ports, port C
as two 4-bit ports

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PPI 8255A - MODES
 Mode 1: I/O with handshake
 I/O data transfer is controlled by handshake signals (i.e. when transfer speeds
are not same, e.g. printer)

Data Bus

STB’
Computer Printer
ACK’

BUSY

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PPI 8255A - MODES
Mode 1 features:
Ports A and B function as 8-bit I/O ports
Each uses 3 lines from port C as handshake

signals, remaining 2 – for simple I/O

functions
 Port A input: uses pins PC3, PC4, PC5
 Port A output: uses pins PC3, PC6, PC7

 Port B I/O : uses pins PC0, PC1, PC2

I/O data are latched

Interrupt logic is supported 29
 PPI 8255A
MODE 1
 Single handshaking (strobed) is used
 Ports A andB function as 8-bit I/O ports
 Each uses 3 lines from port C as handshake
signals, remaining 2 – for simple I/O
functions
 Port A input: uses pins PC3, PC4, PC5
 Port A output: uses pins PC3, PC6, PC7
 Port B I/O : uses pins PC0, PC1, PC2
 I/O data are latched 30
 Interrupt logic is supported
PPI 8255A - MODES
 Mode 1 operation

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 PPI 8255A
MODE 1…
 Mode 1 operation

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 PPI 8255A
MODE 1…
 Input control signal definitions:
 STB (Strobe input):
 Generated by a peripheral device when a peripheral device has some valid data, it
sends a low STB signal.

 IBF (Input buffer full):

 On receipt of STB signal from peripheral device, data is stored in 8255 by its
input latch. In its turn, 8255 generates a high IBF
 IBF is reset when CPU reads the data

 INTR (Interrupt request):

 Generated only if STB , IBF and INTE are all set at the same time. This signal
interrupts the CPU via its INTR pin

 INTE (Interrupt Enable): 33

 This is an internal F/F which can be set/reset using the BSR mode. It must be set
if INTR signal is to be effective.
 PPI 8255A
MODE 1…
 Mode 1 input operation

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 PPI 8255A
MODE 1…
 Output control signal definitions:

 OBF (Output buffer full)

 Indicates that CPU has written data to the specified output port

 ACK (Acknowledge input)

 ACK signal acts as an acknowledgement to be given by an output device
 ACK signal, whenever low, informs the CPU that the data transferred by
the CPU to the output device through the port is received by the output
device

 • INTR (Interrupt request)

 An output signal that can be used to interrupt the CPU when an output
device acknowledges the data received from the CPU.
 INTR is set when ACK, OBF and INTE are 1. It is reset by a falling edge 35
on WR input. The INTEA and INTEB flags are controlled by the bit set-
reset mode of PC6 and PC2 respectively.
 PPI 8255A
MODE 1…
 Mode 1 output operation

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PPI 8255A - MODES
 Mode 2: bi-directional data transfer
 Allows bi-directional data transfer over a single data bus

 Available for port A only

 PC3 – PC7 used for handshaking

 Port B can be programmed in mode 0 or 1

 PC0-PC2 can be used as I/O if port B set to mode 0, handshake if mode 1

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 PPI 8255A
MODE 2
 Allows bi-directional data transfer over a single data
bus
 Available for port A only
 PC3 – PC7 used for handshaking

 Port B can be programmed in mode 0 or 1

 PC0-PC2 can be used as I/O if port B set to mode 0,

handshake if mode 1

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 PPI 8255A
MODE 2…
 Mode 2 operation

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 PPI 8255A
CONTROL WORD FORMATS
 Two control word formats are used:
 Mode set control word format
 To set modes of each port
 Port C bit Set/Reset control word format
 To set particular bit in port C

 These two formats can be differentiated by MSB of the

control word
 Control words can be sent to corresponding 8255’s
address by using I/O instruction
 High on RESET causes all ports to be in I/P mode
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 PPI 8255A
CONTROL WORD FORMATS
 Two control word formats are used:
 Mode set control word format
 To set modes of each port
 Port C bit Set/Reset control word format
 To set particular bit in port C

 These two formats can be differentiated by MSB of the

control word
 Control words can be sent to corresponding 8255’s
address by using I/O instruction
 High on RESET causes all ports to be in I/P mode
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 PPI 8255A
MODE SET CONTROL WORD FORMAT

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 PPI 8255A
PORT C BIT SET/RESET CW FORMAT

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PPI 8255A CONTROL WORD
 Port C bit Set/Reset CW

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 Mode 2: bi-directional data transfer
 Allows bi-directional data transfer over a single data bus

 Available for port A only

 PC3 – PC7 used for handshaking

 Port B can be programmed in mode 0 or 1

 PC0-PC2 can be used as I/O if port B set to mode 0, handshake if

mode 1

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PPI 8255A CONTROL WORD
 Control word (CW) formats
 Highon RESET causes all ports to be in I/P mode
 Two CW formats are used:
 Mode set CW – to set modes of each port
 Port C bit Set/Reset CW – to set particular bit in port C

 These formats can be differentiated by MSB of CW

 CWs can be sent to corresponding 8255’s address by using I/O

instruction

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PPI 8255A CONTROL WORD
 E.g. Assume 8255A is located at FFF8H, control register
address is FFFEH, CW is to be set to 10001110B:
MOV AL, 10001110B
MOV DX, FFFEH
OUT DX, AL

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PPI 8255A CONTROL WORD
 Mode set CW

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PPI 8255A CONTROL WORD
 Port C bit Set/Reset CW

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PPI 8255A CONTROL WORD
 CW example: suppose we want to set:
 Port A as mode 0 output
 Port B as mode 1 input

 Port C upper as inputs

 Port C bit 3 output and set bit 3

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PROGRAMMING PPI 8255A
 The CW programs functionality of ports
 Ports and CW reg map to I/O memory with assigned base
address (e.g. FFF8H)
 PPI addresses:
Port Address Function e.g.
BASE_ADDR Port A FFF8H
“ +1 Port B FFF9H
“ +2 Port C FFFAH
“ +3 Control Register FFFBH

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PROGRAMMING PPI 8255A
 Example: the following program outputs the value 90H
(10010000B) to the control register:
MOV DX, CNTRL_REG ;setup PPI
with
MOV AL, 90H ;port B as
O/P
OUT DX, AL
Exercises: for the ff bit patterns, identify mode of operation:
01101000
10011000

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