OPERATING

SYSTEM: CSET209
  Multilevel paging
 Segmentation
CONTENT
 Segmented paging
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MULTILEVEL PAGING

 Multilevel paging is a paging scheme where there exists a hierarchy of page tables.
 The need for multilevel paging arises when-
 The size of page table is greater than the frame size.
 As a result, the page table can not be stored in a single frame in main memory.
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MULTILEVEL PAGING:
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MULTILEVEL PAGING: WORKING

 The page table having size greater than the frame size is divided into several parts.
 The size of each part is same as frame size except possibly the last part.
 The pages of page table are then stored in different frames of the main memory.
 To keep track of the frames storing the pages of the divided page table, another page table is
maintained.
 As a result, the hierarchy of page tables get generated.
 Multilevel paging is done till the level is reached where the entire page table can be stored in a
single frame.
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ILLUSTRATION OF MULTILEVEL PAGING

 Consider a system using paging scheme where- Number of Frames in Main Memory-

Number of frames in main memory

 Logical Address Space = 4 GB = Size of main memory / Frame size
= 16 TB / 4 KB
 Physical Address Space = 16 TB = 232 frames
Thus, Number of bits in frame number = 32 bits
 Page size = 4 KB

Number of Bits in Page Offset-

Number of Bits in Physical Address-
We have,
Size of main memory Page size
= Physical Address Space = 4 KB
= 16 TB = 212 B
= 244 B Thus, Number of bits in page offset = 12 bits
Thus, Number of bits in physical address = 44 bits
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ILLUSTRATION OF MULTILEVEL PAGING

So, Physical address is-

Inner Page Table Size-

Number of Pages of Process-
Inner page table keeps track of the frames storing the pages of
Number of pages the process is divided process.
= Process size / Page size Inner Page table size
= 4 GB / 4 KB = Number of entries in inner page table x Page table entry size
= 220 pages = Number of pages the process is divided x Number of bits in
frame number
= 220 x 32 bits
= 220 x 4 bytes
= 4 MB
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ILLUSTRATION OF MULTILEVEL PAGING

Number of Page Table Entries in One Page of Inner Page
Number of Pages of Inner Page Table-
Table-
Number of pages the inner page table is divided
Number of page table entries in one page of inner page table
= Inner page table size / Page size
= Page size / Page table entry size
= 4 MB / 4 KB
= Page size / Number of bits in frame number
= 210 pages
= 4 KB / 32 bits
= 4 KB / 4 B
= 210
Number of Bits Required to Search an Entry in One Page of Outer Page Table Size-
Inner Page Table-
Outer page table is required to keep track of the frames storing
One page of inner page table contains 2 10 entries. the pages of inner page table.
Thus, Outer Page table size
Number of bits required to search a particular entry in one page = Number of entries in outer page table x Page table entry size
of inner page table = 10 bits = Number of pages the inner page table is divided x Number of
bits in frame number
= 210 x 32 bits
= 210 x 4 bytes
= 4 KB
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NUMBER OF BITS REQUIRED TO SEARCH AN ENTRY IN OUTER PAGE
TABLE
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SEGMENTATION

 Like Paging, Segmentation is another non-contiguous memory allocation technique.

 In segmentation, process is not divided blindly into fixed size pages.
 Rather, the process is divided into modules for better visualization.
 Segmentation is a variable size partitioning scheme.
 In segmentation, secondary memory and main memory are divided into partitions of
unequal size.
 The size of partitions depend on the length of modules.
 The partitions of secondary memory are called as segments
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SEGMENTATION: EXAMPLE
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SEGMENT TABLE

 Segment table is a table that stores the information about each segment of the process.
 It has two columns.
 First column stores the size or length of the segment.
 Second column stores the base address or starting address of the segment in the main memory.
 Segment table is stored as a separate segment in the main memory.
 Segment table base register (STBR) stores the base address of the segment table.
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SEGMENT TABLE
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SEGMENT TABLE
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TRANSLATING LOGICAL ADDRESS INTO PHYSICAL ADDRESS

•CPU always generates a logical address.

•A physical address is needed to access the main memory.

Step-01:

CPU generates a logical address consisting of two parts-

1.Segment Number
2.Segment Offset
•Segment Number specifies the specific segment of the process from which CPU wants to read the data.
•Segment Offset specifies the specific word in the segment that CPU wants to read.
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TRANSLATING LOGICAL ADDRESS INTO PHYSICAL ADDRESS

Step-02: For the generated segment number, corresponding entry is located in the segment table.
Then, segment offset is compared with the limit (size) of the segment.
Now, two cases are possible-

Case-01: Segment Offset >= Limit

If segment offset is found to be greater than or equal to the limit, a trap is generated.
Case-02: Segment Offset < Limit
• If segment offset is found to be smaller than the limit, then request is treated as a valid request.
• The segment offset must always lie in the range [0, limit-1],
• Then, segment offset is added with the base address of the segment.
• The result obtained after addition is the address of the memory location storing the required word.
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TRANSLATING LOGICAL ADDRESS INTO PHYSICAL ADDRESS

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TRANSLATING LOGICAL ADDRESS INTO PHYSICAL ADDRESS

Advantages-

The advantages of segmentation are-

•It allows to divide the program into modules which provides better visualization.
•Segment table consumes less space as compared to page table in paging.
•It solves the problem of internal fragmentation.

Disadvantages-

The disadvantages of segmentation are-

•There is an overhead of maintaining a segment table for each process.
•The time taken to fetch the instruction increases since now two memory accesses are required.
•Segments of unequal size are not suited for swapping.
•It suffers from external fragmentation as the free space gets broken down into smaller pieces with
the processes being loaded and removed from the main memory.
 EXAMPLE

CONSIDER THE FOLLOWING SEGMENT TABLE-

Segmen
Limit Base
t No.

0 700 1219
1 14 2300
2 100 90
3 580 1327
Which of the following logical address will produce trap
4 96 1952
addressing error?

A. 0, 430
B. 1, 11
C. 2, 100
D. 3, 425
E. 4, 95
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CONSIDER THE FOLLOWING SEGMENT TABLE-

Segmen
Limit Base
t No.

0 700 1219
1 14 2300
2 100 90
3 580 1327
Which of the following logical address will produce trap
4 96 1952
addressing error?

A. 0, 430
B. 1, 11
C. 2, 100
D. 3, 425
E. 4, 95

Calculate the physical address if no trap is produced.

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SEGMENTATION AND PAGING

Segmented paging is a scheme that implements the combination of segmentation and paging.

• Process is first divided into segments and then each segment is divided into pages.
• These pages are then stored in the frames of main memory.
• A page table exists for each segment that keeps track of the frames storing the pages of that segment.
• Each page table occupies one frame in the main memory.
• Number of entries in the page table of a segment = Number of pages that segment is divided.
• A segment table exists that keeps track of the frames storing the page tables of segments.
• Number of entries in the segment table of a process = Number of segments that process is divided.
• The base address of the segment table is stored in the segment table base register.
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TRANSLATING LOGICAL ADDRESS INTO PHYSICAL ADDRESS

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TRANSLATING LOGICAL ADDRESS INTO PHYSICAL ADDRESS

Advantages-

The advantages of segmented paging are-

• Segment table contains only one entry corresponding to each segment.

• It reduces memory usage.
• The size of Page Table is limited by the segment size.
• It solves the problem of external fragmentation.

Disadvantages-

The disadvantages of segmented paging are-

• Segmented paging suffers from internal fragmentation.

• The complexity level is much higher as compared to paging.
Thankyou