NMK10803 –

Digital Systems

1
Combinational Logic Circuits

Disclaimer:
•Most of the contents (if not all) are extracted from resources available
for Digital Fundamentals 10th Edition

2
Refresh Combinational Logic
Circuit
A B C OUTPUT
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0
A B C D Y
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 Draw the logic
0 1 0 1 1
circuit diagram
0 1 1 0 1
0 1 1 1 1
for output Y
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0
Half-
Adder
Basic rules of binary addition are performed by a
half adder, which has two binary inputs (A and
B) and two binary outputs (Carry out and Sum).
The inputs and outputs can be summarized on a
truth table.

The logic symbol and equivalent circuit are:

Σ Σ
A Σ
A
Cout
B Cout B

5
Full-Adder

By contrast, a full adder has three binary

inputs (A, B, and Carry in) and two binary
outputs (Carry out and Sum). The truth table
summarizes the operation.
A full-adder can be constructed from two
half adders as shown:
Σ Σ
A A Σ A Σ Sum
Σ
B B Cout B Cout A Σ
B
Cout
Cin Cin

Cout
Symbol
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Full-Adder Σ Σ 0 Sum
1 A Σ 1 A Σ
Example
0 B Cout 0 B Cout 1

For the given inputs, determine 1

Cout
the intermediate and final outputs 1
of the full adder.
The first half-adder has inputs of 1 and 0;
therefore the Sum =1 and the Carry out = 0.
The second half-adder has inputs of 1 and 1; therefore the
Sum = 0 and the Carry out = 1.
The OR gate has inputs of 1 and 0, therefore the final carry
out = 1.

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Full-Adder
Notice that the result from the previous example can be
read directly on the truth table for a full adder.

Σ Σ 0 Sum
1 A Σ 1 A Σ

0 B Cout 0 B Cout 1

1 Cout
1

8
Parallel
Adders
Full adders are combined into parallel adders that can add binary
numbers with multiple bits. A 4-bit adder is shown.
A4 B4 A3 B3 A2 B2 A1 B1

C0

A B Cin A B Cin A B Cin A B Cin

Cout Σ Cout Σ Cout Σ Cout Σ

C4
C3 C2 C1
Σ4 Σ3 Σ2 Σ1

The output carry (C4) is not ready until it propagates through all of the
full adders. This is called ripple carry, delaying the addition process.

9
Parallel
Adders
The logic symbol for a 4-bit parallel adder is shown. This 4-bit adder
includes a carry in (labeled (C0) and a Carry out (labeled C4).
Σ
1 1
Binary 2 2 4-bit
number A 3 3 sum
4 4
1
Binary 2
number B 3
4
Input Output
C0 C4
carry carry

The 74LS283 is an example. It features look-ahead carry, which adds

logic to minimize the output carry delay. For the 74LS283, the
maximum delay to the output carry is 17 ns.

10
Comparator
s The function of a comparator is to compare the magnitudes of two
binary numbers to determine the relationship between them. In the
simplest form, a comparator can test for equality using XNOR gates.
How could you test two 4-bit numbers for equality?
Example
AND the outputs of four XNOR gates.
A1
B1
A2
B2 Output
A3
B3
A4
B4

11
Comparator
s IC comparators provide outputs to indicate which of the numbers is
larger or if they are equal. The bits are numbered starting at 0, rather
than 1 as in the case of adders. Cascading inputs are provided to
expand the comparator to larger numbers.

COMP
A0 0
A1 A
A2
A3 3
Cascading A>B A>B
A=B A=B Outputs
inputs
A<B A<B
B0 0
B1 A
The IC shown is the
B2
B3 3 4-bit 74LS85.

12
Comparator
s IC comparators can be expanded using the cascading inputs as
shown. The lowest order comparator has a HIGH on the A = B input.
LSBs MSBs

A0 COMP A4 COMP
A1 0 A5 0
A2 A A6 A
A3 A7
3 3
A>B A>B A>B A>B
+5.0 V A=B A=B A=B A=B Outputs
A<B A<B A<B A<B
B0 0 B4 0
B1 A B5 A
B2 B6
B3 3 B7 3

13
Decoders
A decoder is a logic circuit that detects the presence of a specific
combination of bits at its input. Two simple decoders that detect the
presence of the binary code 0011 are shown. The first has an active
HIGH output; the second has an active LOW output.

A0 A0
A1 X A1 X

A2 A2

A3 A3

Active HIGH decoder for 0011 Active LOW decoder for 0011

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Decoders

Assume the output of the decoder shown is a

Try This!
logic 1. What are the inputs to the decoder?

15
Decoders
IC decoders have multiple outputs to decode any
combination of inputs. For example, the binary-to-decimal
decoder shown here has 16 outputs – one for each
combination of binary inputs.
Bin/Dec
0
For the input shown, 1
2
Try This! what is the output? 3
4
1 A0 5
6
4-bit binary 1 A1 7 Decimal
input 0 A2 8 outputs
9
1 A3 10
11
12
13
14
15

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Decoders
X/Y
A specific integrated circuit
decoder is the 74HC154 (shown as
a 4-to-16 decoder). It includes two
active LOW chip select lines which A0
must be at the active level to enable A1
A2
the outputs. These lines can be used A3
to expand the decoder to larger
inputs.

CS1
CS2 EN
74HC154

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• Another decoder IC is 74LS138
Checkpoint
–a 3-8 decoder (active low output)
–3 'enable' bits (G1 - active high, /G2A
& /G2B – active low)
• Let a 3-bit counter (output C2C1C0) to be used as input to a
74LS138 IC

–assume all enable bits asserted

–sketch the output if counter is counting
up

18
Decoders

BCD-to-decimal decoders accept a binary A0

coded decimal input and activate one of ten A1
A2
possible decimal digit indications.
A3

Assume the inputs to the 74HC42

Example decoder are the sequence 0101, 0110,
0011, and 0010. Describe the output.

All lines are HIGH except for one active output, which
is LOW. The active outputs are 5, 6, 3, and 2 in that
order.

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BCD Decoder/Driver
Another useful decoder is the 74LS47. This is a BCD-to-
seven segment display with active LOW outputs.
VCC

BCD/7-seg
The a-g outputs are BI/RBO BI/RBO
designed for much
higher current than most BCD Outputs
devices (hence the word inputs to seven
segment
driver in the name). device
LT LT
RBI RBI

74LS47

GND

20
BCD Decoder/Driver
Here the 7447A is an connected to an LED seven segment
display. Notice the current limiting resistors, required to
prevent overdriving the LED display.

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BCD Decoder/Driver
The 74LS47 features leading zero suppression, which
blanks unnecessary leading zeros but keeps significant
zeros as illustrated here. The BI/RBO output is connected
to the RBI input of the next decoder.

Blanked Blanked Depending on the display type, current

limiting resistors may be required.

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BCD Decoder/Driver
Trailing zero suppression blanks unnecessary trailing
zeros to the right of the decimal point as illustrated here.
The RBI input is connected to the BI/RBO output of the
following decoder.

Decimal Blanked Blanked

point

23
Encoders
An encoder accepts an active logic level on one of its
inputs and converts it to a coded output, such as BCD or
binary.
1
The decimal to BCD is an encoder A0
with an input for each of the ten 2

decimal digits and four outputs that 3

A1
represent the BCD code for the active
4
digit. The basic logic diagram is 5 A2
6
shown. There is no zero input 7
because the outputs are all LOW 8
A3
when the input is zero. 9

24
Encoders
Show how the decimal-to-BCD encoder converts the
decimal number 3 into a BCD 0011.
Example The top two OR gates have ones as indicated by
the red lines. Thus, the output is 0011.

1 0 1
A0
2 0
1
3 1
A1

4 0
5 0 0
6
0
0 A2
7
8 0 0
A3
0
9

25
Encoders
The 74HC147 is an example of an IC encoder. It is has ten
active-LOW inputs and converts the active input to an
active-LOW BCD output. V CC

This device is offers additional HPRI/BCD

flexibility in that it is a priority

encoder. This means that if more
than one input is active, the one Decimal BCD
with the highest order decimal input output

digit will be active.

74HC147
The next slide shows an application … GND

26
 VCC

Encoders
Keyboard
encoder HPRI/
BCD

BCD complement of
key press

74HC147

The zero line is not needed by the

encoder, but may be used by other
circuits to detect a key press.

27
 Checkpoint
• Gray code (reflected binary code)
–only 1 bit changes between 2 successive value
–very useful for error detection/correction

2-bit Gray 3-bit Gray

Code Code
00 000
01 001
11 011
10 010
110

111

101

100

28
Code converters
There are various code converters that change one code to
another. Two examples are the four bit binary-to-Gray
converter and the Gray-to-binary converter.
Show the conversion of binary 0111 to Gray and back.
Try This! 0 1 LSB
1 0
LSB
0 1
1 0

1 1 1 1

0 0
0 MSB 0 MSB
Binary-to-Gray Gray-to-Binary

29
Multiplexers
A multiplexer (MUX) selects one data line from two or
more input lines and routes data from the selected line to
the output. The particular data line that is selected is
determined by the select inputs.
Two select lines are shown 0
S0
Data 1
here to choose any of the select S1
four data inputs.
D0 Data
Try This! Data
D1 output
D
inputs D2
Which data line is selected 3

if S1S0 = 10?

30
Demultiplexer
s
A demultiplexer (DEMUX) performs the opposite function
from a MUX. It switches data from one input line to two or
more data lines depending on the select inputs.
The 74LS138 was introduced
previously as a decoder but can also
Data
serve as a DEMUX. When select
connected as a DEMUX, data is lines
Data
applied to one of the enable inputs, outputs
and routed to the selected output Enable
line depending on the select inputs
variables. Note that the outputs are
active-LOW as illustrated in the 74LS138
following example…

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 A0
A1
Demultiplexer
A2
s Determine the outputs, given the
inputs shown. G1
Try This! G2A LOW
The output logic is opposite to the input G2B LOW
because of the active-LOW convention. (Red
shows the selected line). Y0
Y1
Data Y2
select
lines
Data
Y3
outputs Y4
Enable
Y5
inputs
Y6
74LS138 Y7
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 Quiz
For the full-adder shown, assume the input bits are as shown
with A = 0, B = 0, Cin = 1. The Sum and Cout will be
a. Sum = 0 Cout = 0
Σ Σ Sum
0 A Σ A Σ
b. Sum = 0 Cout = 1
0 B Cout B Cout
c. Sum = 1 Cout = 0
1
d. Sum = 1 Cout = 1 Cout

33
 Quiz
The output will be LOW if
a. A < B A1
B1
b. A > B A2 Output
B2
c. both a and b are A3
correct B3
A4
d. A = B B4

34
 Quiz
If you expand two 4-bit comparators to accept two 8-bit
numbers, the output of the least significant comparator is
a. equal to the final output
b. connected to the cascading inputs of the most
significant comparator
c. connected to the output of the most significant
comparator
d. not used

35
 Quiz
Assume you want to decode the binary number 0011 with an
active-LOW decoder. The missing gate should be
a. an AND gate A0
X
b. an OR gate
A1
?
A2
c. a NAND gate
A3
d. a NOR gate

36
 Quiz
Assume you want to decode the binary number 0011 with an
active-HIGH decoder. The missing gate should be
a. an AND gate A0
X
b. an OR gate
A1
?
A2
c. a NAND gate
A3
d. a NOR gate

37
 Quiz
The 74138 is a 3-to-8 decoder. Together, two of these ICs can
be used to form one 4-to-16 decoder. To do this, connect
a. one decoder to the LSBs of the input; the other
decoder to the MSBs of the input
b. all chip select lines to ground
c. all chip select lines to their active levels
d. one chip select line on each decoder to the input MSB

38
 Quiz
The decimal-to-binary encoder shown does not have a zero
input. This is because
a. when zero is the input, 1
A0
all lines should be LOW 2
3
A1
b. zero is not important
4
5 A2
c. zero will produce 6
7
illegal logic levels 8
A3
9
d. another encoder is used
for zero

39
 Quiz
If the data select lines of the MUX are S1S0 = 11, the output
will be
a. LOW
S0
Data
b. HIGH select S1

c. equal to D0 D0 Data
D output
Data D1
d. equal to D3 inputs D2
3

40
 Quiz
The 74138 decoder can also be used as
a. an encoder
b. a DEMUX
c. a MUX
d. none of the above

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