Kadapa Rajashekhar

ECE1902 Industrial Internship Reddy

21bec1496

AHB to APB Bridge

Design
using Verilog HDL
INDUSTRY COMPLETE ADDRESS & CONTACT PERSONS
WITH PHONE NUMBERS

Address: 21/1A, III Floor, Marudhar Avenue, Gottigere Uttarahalli Hobli, South
Taluk, Bannerghatta Main Rd, Bengaluru, Karnataka 560076

Contact: 080 6909 6300

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Certificate

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Agenda
 Objective of the Training
 Overview of the Project
 Proposed system
 Read and Write Transfers
 Results and discussions
 Conclusion
 References

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 Objective of the Training

AHB AHB to APB Bridge APB

The VLSI Design Methodologies Course by MAVEN SILICON provided an

overview of VLSI and explains various VLSI technology

Following project assignment, each student received project-specific

training. In this case, detailed concepts of AMBA (Advanced
microcontroller bus architecture), AHB (Advanced high-performance bus),
APB (Advanced peripheral bus), and the bridge are used. After receiving
adequate training, students were able to design each and every aspect of the
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bridge that converts AHB to APB using Verilog HDL.
 Overview of the Project
The goal of this project, is to develop a synthesizable design of AHB2APB bridge
A complex interface bridge between the Advanced High-Performance Bus (AHB) and
the Advanced Peripheral Bus (APB)

AHB to APB bridge is a standard bus-to-bus interface that helps to bridge

the communication gap between a high performance, high clock frequency,
large bandwidth Advanced High-performance Bus AHB and a low clock
frequency, minimal power consuming Advanced peripheral bus APB.
Another importance of constructing a bridge is to avoid data loss when data
transfer is initiated.

The high-speed AHB and the low-power APB are connected via the AHB to
APB bridge, an AHB slave. Transfers from the AHB's read and write
operations are translated into similar transfers on the APB. Wait states are
introduced during transfers to and from the APB when the AHB is required
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to wait for the APB because the APB is not pipelined.

Proposed System
• The AHB to APB bridge acts as a translation layer
between the two buses, enabling seamless
communication and data transfer between AHB masters
and APB slaves.

• It allows AHB masters to access and control the APB

peripherals by converting the AHB transactions into
corresponding APB transactions and vice versa.

• When an AHB master initiates a read or write

transaction targeting an APB peripheral, the AHB to
APB bridge translates the transaction into an
appropriate APB transaction, incorporating the
necessary control signals, addressing, and data.
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AHB Master:

An AHB (Advanced High-performance Bus) master refers to a component or device in a computer

system that is capable of initiating data transactions which can include reading from or writing to
memory-mapped registers, accessing peripherals, or interacting with other components in the system
and controlling data transfers on an AHB bus. It generates the appropriate control signals and
addresses to access specific devices or memory locations on the bus.

AHB Slave Interface:

The AHB (Advanced High-Performance Bus) slave interface is a module that allows a device or
peripheral to be connected to an AHB bus in a computer system. When a peripheral device or memory
is designated as an AHB slave, it means that it can respond to read or write requests initiated by AHB
masters on the bus. The AHB slave interface is responsible for receiving and processing these
requests, as well as returning the requested data or performing the necessary write operation.

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APB Controller

The APB controller acts as an interface between the AHB bus and the APB peripherals, enabling them
to communicate with the rest of the system. It manages the data transfer and control signals between
the AHB and APB buses, translating the AHB transactions into APB-compatible signals and vice
versa. The APB controller is responsible for managing the data transfers and control signals between
the APB bus and the connected peripherals.

APB Interface:

An APB (Advanced Peripheral Bus) interface refers to the connection and protocol used by peripheral
devices or controllers that are connected to an APB bus. The APB interface defines the signals,
timings, and protocols used for communication between the peripheral devices and the APB bus. It
enables the peripheral devices to receive commands, send and receive data, and provide status
information to the system.

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 Transfers
 Single Read Transfer
 Single Write Transfer
 INCR Burst Read Transfer
 WRAP Burst Read Transfer
 INCR Burst Write Transfer
 WRAP Burst Write Transfer

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 Single Read Transfer
A "single read transfer" refers to the process of reading a single piece of data from a memory location or a peripheral device in the
microcontroller. In AHB to APB conversion, AHB initiates a transfer when it wishes to read data (eg., single byte or single word)
from an APB slave.

 Request: AHB initiates a request to read data from a specific address and asserts appropriate signals to indicate a read operation.

 Address Phase: The address information is transferred from the AHB master to the APB slave during this phase. The APB slave
decodes the address and identifies the location from which the data is to be read.

 Data Transfer Phase: Once APB master sends the read request to the target peripheral connected to the APB bus. The target
peripheral processes the read request, accesses the data and provides the requested data. The data is transferred from target
peripheral to APB master over APB bus.

 Response Phase: The APB master after receiving the data from the targeted peripheral acknowledges the data reception and
prepares to send data back to the bridge. Bridge Translates the data received from APB bus back into AHB format.

 Data Utilization Phase: The AHB master which initiates the read request, receives the translated data from the bridge. Now it can
utilize the data for its intended purpose, such as performing calculations, updating registers, or processing data as needed.

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Single Read Transfer

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 Single Write Transfer
A "single write transfer refers to a single operation of storing a single piece of data at a specific memory address or a designated location
within a system.

• Request: controller, initiating a write request. The master specifies the address in AHB address space where it wants to write data.
The process begins with an AHB master, such as a CPU or DMA

• Address Phase: The APB slave decodes the address and identifies the location where the data is to be written .

• Data Transfer: The actual data to be written is transferred from the AHB master to the APB slave. The target peripheral processes
the write request and stores the provided data in its location on the APB bus.

• Response Phase: The APB master acknowledges the data reception and response to the write request, indicating whether the write
operation was successful.

• Data Utilization Phase: The AHB master, which originally initiated the write request, can utilize the written data on the APB
peripheral for its intended purpose. This might include configuration settings, data transfer commands, or any other operation
required

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Single Write Transfer

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 Burst Write Transfer
 Burst write transfers enable efficient and continuous writing of multiple data items from an AHB master to an APB slave within a
system-on-chip (SoC) design.

 In a burst write transfer, data elements are written sequentially, one after the other, to contiguous memory locations or registers.

 In an INCR (Incrementing) burst write transfer, consecutive data elements are written to memory locations or registers with
sequentially increasing addresses. The address for the first data element is specified, and subsequent data elements are written to
memory locations with addresses that increase by a fixed amount with each write.

 In a WRAP (Wrapping) burst write transfer, consecutive data elements are written to memory locations or registers, similar to
INCR bursts. However, when the address reaches the maximum address in the address space, it wraps around to the beginning and
continues writing data. This means that the burst can "wrap" around to the start of the memory space once the end is reached,
allowing for circular buffer-like behaviour. WRAP bursts are useful in applications where you need to continuously write data in a
circular manner, like circular buffers or ring buffers.

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INCR Burst Write Transfer

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WRAP Burst Write Transfer

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 Burst Read Transfer
 Burst read transfers allow for efficient and continuous reading of multiple data items from an AHB master to an APB slave. In a
burst read transfer, data elements are read sequentially, one after the other, from contiguous memory locations or registers. Burst
read transfers are efficient because they reduce the overhead associated with address setup and data transfer for each element,
which is common in single read transfers.

 In an INCR burst read transfer, consecutive data elements are read from memory locations or registers with sequentially
increasing addresses. The address for the first data element is specified, and subsequent data elements are read from memory
locations with addresses that increase by a fixed amount with each read. INCR bursts are typically used when you want to read data
from contiguous memory locations and take advantage of sequential addressing.

 In a WRAP burst read transfer, consecutive data elements are read from memory locations or registers, similar to INCR bursts.
However, when the address reaches the maximum address in the address space, it wraps around to the beginning and continues
reading data. This means that the burst can "wrap" around to the start of the memory space once the end is reached, allowing for
circular buffer-like behaviour. WRAP bursts are useful in applications where you need to continuously read data in a circular
manner, such as circular buffers or ring buffers.

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INCR Burst Read Transfer

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WRAP Burst Read Transfer

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 Conclusion
AHB to APB Bridge was successfully designed which ensures seamless communication and data transfer with
efficiency, flexibility, and dependability between the Advanced High-Performance Bus (AHB) and the Advanced
Peripheral Bus (APB).

They help maintain efficient data flow while preserving the integrity and functionality of both the AHB and APB
buses.

AHB2APB bridge design is implemented in Verilog HDL for Read transfer, write transfer, read burst transfer,
write burst transfer which provides all the necessary fundamental capabilities of data communication between
AHB and APB.

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 Learning Outcome

 Understanding of AMBA Architecture

 Design and working of AHB to APB Bridge

(How to interface AHB and APB bus)

 Knowledge of various data transfers.

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 Future Scope
 AI and ML are becoming increasingly important in embedded systems. AHB to APB
Bridges may need to support data transfer and communication between AI
accelerators and other components
 AHB to APB Bridge may play a crucial role in connecting sensor peripherals and
other IOT components to high performance processing cores.
 Future AHB to APB bridges may incorporate security features to protect data and
prevent unauthorized access to peripherals

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 References
[1] https://elearn.maven-silicon.com/vlsi-design-course

[2] Pal, G. and Mohan, R., 2012. Design of ahb2apb ridge for efficient utilization of ahb and apb. ISSN:
2320- 9984 International Journal of Modern Engineering & Management Research, 1(4).

[3] Rao, N.V., Chandrika, P.V., Kumar, A. and Reddy, S., 2020. Design of AMBA based AHB2APB protocol
for efficient utilization of AHB and APB. International Research Journal of Engineering and Technology
(IRJET), 7(03), pp.2395-0072.

[4] Vani.R.M † and M.Roopa ††,”Design of AMBA Based AHB2APB Bridge Vani.R.”, IJCSNS International
Journal of Computer Science and Network Security, VOL.10 No.11, November 2010

[5] https://developer.arm.com/documentation/ddi0243/c/AHB-Components/APB-bridge

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Thank You
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