Bistable elements

Bistable elements(latches and flipflop) exhibits two stable states. The are capable of residing in either of these two states indefinitely. The two states are called SET and RESET. Because of their ability to retain a given state,bistable elements are useful as storage (memory) devices.
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Bistable elements contd...

The flip-flop is a bistable logic circuit which is a type of Multivibrator. There are 4 basic categories of bistable elements: the latch,the edge-triggered flipflop,the pulse-triggered (master-slave) flip-flop,and the data lockout flip-flop. The flip-flop is a basic building-block for register, memories, counters,control logic,and other function in digital systems.
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Latch
The latch is a type of bistable device Latches are basically similar to flipflops because they are bistable devices that can reside In either of two states by virtue of a feedback arrangement. The main difference between latches and flip-flops is in the method used for changing their state.
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S-R Latch
An active-low input SR latch is formed with two cross-coupled NAND gates as shown in fig. Notice that the output of each gate is connected to an input of the opposite gate. This produces the feedback that is characteristic of all multivibrators.
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Active-Low input S-R latch.

S

Q R

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Operation(for active-low input S-R latch) When both inputs are high there will be no change in the output i.e. flipflop will remain in the present state. When S is low and R is kept high latch will set. When S is high and R is low ,latch will reset. When both inputs are low , there will be a invalid condition.
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Truth table for an active-low input S - R latch

Inputs

outputs

S
1 0 1

R 1 1 0

Q
NC 1 0 1

Q
NC 0 1

Comments
No change. Latch remains In present state. Latch SETS. Latch RESETS. Invalid condition

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Timing diagram for active low input SR latch

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FLIP-FLOP
A flip flop is a bistable electronic circuit that has two stable states, --I.e. its output ie either 0 or +5 volts dc The flip - flop also has memory. For instance, when the flip - flop has its output set at 0 V dc, it can be regarded as storing a logic 0 and when its output is set at +5 V dc, as storing a logic 1.
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FLIP-FLOP
Flip - flops are synchronous devices The term edge-triggered means that the flip-flop changes state either at the positive edge or at the negative edge of the clock pulse. Flip-flop is sensitive to its inputs only at this transition of the clock. Three basic types of edge-triggered flip-flops are S-R, D and J-K flip-flop.
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The Edge-Triggered S-R flip-flop

Logic symbol flip-flop using NAND gate
S clk Q R Q Q

S clk R

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Truth table for positive edge-triggered S-R flip-flop

Inputs S
0 0 1 1

Outputs
Comments

R
0 1 0

C
X

Q Q
0 1 Invalid

Q
1 0

No change Reset

Set
Invalid

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Function of S R flip-flop
The S and R inputs of the S-R flipflop are called the synchronous inputs. When S is high R is low, the Q output goes high on the triggering edge of the clock pulse and the flipflop is set. When S is low and R is high, the q output goes and the flip-flop is reset.
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Function of S R flip-flop
When both S and R low, the output does not change from its prior state. An invalid condition exists when both S and R are high.

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Timing Diagram
clk 1 2 3 4 5

S R

Q Q

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Delay Flip - flop(D flip-flop)

The D flip - flop is very useful when a single data bit(1 or 0 ) is to be stored.
D Q

clk

D flip-flop

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Function of D flip-flop

If there is a high in the D input when a clock pulse is applied, the flip-flop will SET,and the high on the D input is stored by the flip-flop in the positive leading edge of the clock pulse. If there is a low on the D input when clock pulse is applied, the flip-flop will reset, and low on the D input is stored by the flip-flop on the leading edge of the clock pulse.
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Truth table for D flip-flop

Inputs D C

Outputs Comments Q Q

Set (stores a 1)

Reset (stores a 0)

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Timing Diagram
clk 1 2 3 4 5

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J-K flip-flop
The J-K flip-flop is very versatile and is perhaps the most widely used type of flip-flop. The functioning of the J-K flip-flop is identical to that of the S-R flip-flop in SET,RESET, and no-change conditions of operation. The difference is that the J-K flip-flop has no invalid state as does the S-R flip-flop.
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JK flip-flop
J clk Q

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Truth-Table
J
0

K 0

clk

Q Q

Q Q 1 0
Q
21

0 1 1
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1
0

0
1 Q
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Operation of JK Flip-flop

When J and K are both low, both AND gates are disabled, clock pulses have no effect and Q retains last value. When J is high and K is low, the flip-flop will set. When J is low and K is high, the flip-flop will reset.
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Operation of JK Flip-flop
When J and K are both high , the flip-flop will toggle. Toggle means to switch to the opposite state. Propagation delay prevents the JK flip-flop from racing(toggling more than once in a clock).
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Timing diagram for JK-flip flop

clk J K Q

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Prevention of racing
Propagation delay prevents the JK flip-flop from racing. Racing can be prevented by using JK Master-slave flip-flop The basic idea in the masterslave flip-flop is the slave copies the master on the negative clock edge.
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JK Master-slave flip-flop

J
clk master

slave
Q

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T flip-flop
The T flip-flop derives its name from its operation, which is toggle. The word implies a change of state when the T input is asserted.
Truth table

T flip-flop T FLIP-FLOP

Q 0 1

clk

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Timing diagram for T-flipflop

clk T Q

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Operating Characteristics
1)Propagation Delay tPLH measured from the triggering edge of the clock pulse to the LOW-TO-HIGH transition of the output.
50% point on triggering edge

50% point on LOW-to-HIGH transition of Q

tPLH
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Operating Characteristics contd..

1)Propagation delay tPHL measured from the triggering edge of the clock pulse to the HIGH-to-LOW transition of the output.
c Q
50% point on HIGH -to-LOW transition of Q

tPHL
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Operating Characteristics contd..

3)Propagation delay tPLH measured from the preset input to the LOW-toHIGH transition of the output.
PRE 50% point

50% point

tPLH
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Operating Characteristics contd..

4)Propagation delay tPHL measured from the clear input to the HIGH-toLOW transition for the output.

CLR
Q

50% point

50% point

tPHL
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Operating Characteristics contd..

Set-Up Time(ts) is the minimum interval
required for the control levels to be maintained constantly on the inputs of a flip-flop prior to the triggering edge of the clock pulse
D 50% point

50% point of triggering edge

ts
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Operating Characteristics contd..

Hold Time (th) is minimum interval required for the control levels to remain on the inputs after the triggering edge of the clock.
D 50% point

50% point on triggering edge

th
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Basic Flip-flop application

1)Parallel data storage 2)Data transfer 3)Frequency division 4)Digital counters

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Flip-flop conversion
Convert the S R flip-flop to a D flip-flop. The model used to convert one flipflop to another is as follows.
Q Flip-flop conversion logic Given

flip-flop

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Conversion Table
Qn 0 Qn + 1 0 1 0 DL 0

Qn 0 0
1

S 0 1 0 X

R X 0 1 0

0
1 1

1
0 1

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The SET RESET conversion map

D Q 0 1 0 1 Q

D 0 0 1

X 0
R=D

0
0

0
S=D

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The circuit conversion fo RS to a D flip-flop

D

R Q

D
Q

=
Q Q

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GLOSSARY
Bistable :- Having two stable states. Buffer Register :- A group of memory elements,often flip-flops, that can be store a binary word. Edge Triggering :- A electronic circuit that has two stable state. Hold Time:- The minimum amount of time that data must be present after the clock trigger arrives.
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GLOSSARY contd..
Setup Time:-The minimum amount of time that data must be present before the clock trigger arrives. Propagation Delay:- The amount of time it takes for the output to change states after an input trigger. Synchronous :- When outputs change states in time with a clock. Fan-in:- It is used to define no. of inputs of a gate. Version 1.0 5/2/2012 VHDL Training 41

GLOSSARY contd..
Fan-out:- It is used define no. output of a gate. Asynchronous:- Independent of clocking. The output can change without having to wait for a clock pulse. Schmitt Trigger:- A bistable circuit used to produce a rectangular output waveform.
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Exercises
1) Convert RS flip-flop to T flip-flop 2) Convert RS flip-flop to JK flip-flop 3) Convert JK flip-flop to D flip-flop 4) Convert D flip-flop to JK flip-flop 5)Convert JK flip-flop to RS flip-flop

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State diagram for JK Flip-flop

JK=0,1 J,K=1,0 JK=0,0 JK=0,1

SET
JK=1,1 JK=1,0

RESET

JK=1,1

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