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CM305

The document discusses a lecture on 4-bit synchronous counters. It describes how synchronous counters use a common clock signal to toggle flip-flops simultaneously. The lecture explains the logic circuit and timing diagram of a 4-bit synchronous counter. It also discusses the counter's operation by walking through the changing states with each clock pulse. Advantages of synchronous counters like higher speed and fewer gates are highlighted.

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42 views

CM305

The document discusses a lecture on 4-bit synchronous counters. It describes how synchronous counters use a common clock signal to toggle flip-flops simultaneously. The lecture explains the logic circuit and timing diagram of a 4-bit synchronous counter. It also discusses the counter's operation by walking through the changing states with each clock pulse. Advantages of synchronous counters like higher speed and fewer gates are highlighted.

Uploaded by

api-3853441
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 25

Department of Technical Education

Andhra Pradesh

Name : P. Srinivasa Rao


Designation : Lecturer
Branch : Electronics & Communication Engg.
Institute : Andhra Polytechnic, Kakinada
Year/Semester : III semester
Subject : Digital Electronics
Subject code : CM-305
Topic : Counters & Registers
Duration : 50mts
Sub topic : Synchronous Counter
Teaching Aids : PPT. Diagrams
CM305.52 1
OBJECTIVES

On completion of this period, you would be


able to Know

• Operation Of 4 bit synchronous counter

• Changing of output state according to input

• Timing diagram of synchronous counter

CM305.52 2
Recap
• Logic diagram of 4-bit synchronous
counter

CM305.52 3
• The basic operation can be illustrated from its
timing diagram

CM305.52 4
Note the following :

• QA changes on each clock from its original state to final


state and vice-versa.

• If QA=1 and a clock pulse occurs, FF2 is in the toggle


mode.

• When QA=0, FF2 is in no change mode and remains in


its present state.

• If QA=QB=1 then FF3 output QC is made to change its


state by G1 and JK inputs of FF3.

CM305.52 5
OPERATION

• Let the counter is initially in RESET.

• The output of the counter is given by Q=QDQCQBQA i.e.,


Q=0000.

• The first Flip flop must be the in the toggle mode by


constant high on its J and K inputs. Then QA=1.

CM305.52 6
TRUTH TABLE

CM305.52 7
CM305.52 8
• When the first clock pulse arrives, the FF1 output goes from
0 to 1.

• The output of the counter is Q=0001.

• When the second clock pulse arrives, the first and second
Flip flops toggle. (since J=K=1)

CM305.52 9
• Thus the FF1 goes from 1 to 0 and FF2 goes from 0 to 1.

• The output of the counter is given by


Q=0010.

CM305.52 10
• When the third clock pulse arrives FF1 toggles from
0 to1.

• The output is given by Q=0011

• When forth clock pulse occurs the FF1 and FF2 goes
from 1 to 0 and FF3 goes from 0 to 1.

CM305.52 11
• The output is given by Q=0100.

• When the fifth clock pulse occurs the output is given by


Q=0101.

CM305.52 12
• When the sixth clock pulse occurs the output is given by
Q=0110.

• When the seventh clock pulse occurs the output is given by


Q=0111.

• When the eighth clock pulse occurs the output is given by


Q=1000.

• When the ninth clock pulse occurs the output is given by


Q=1001.

CM305.52 13
• When the tenth clock pulse occurs the output is given by
Q=1010.

• When the eleventh clock pulse occurs the output is


given by Q=1011.

• When the twelth clock pulse occurs the output is given


by Q=1100.

• When the thirteenth clock pulse occurs the output is


given by Q=1101.

CM305.52 14
• When the fourteenth clock pulse occurs the output is
given by Q=1110.

• When the fifteenth clock pulse occurs the output is


given by Q=1111.

• Whenever QA=QB=QC=1, FF4 changes only twice in the


sequence.

CM305.52 15
• Above condition is detected by G2.

• When the clock pulse occurs FF4 changes its state.

• For all other times the J&K inputs of FF4 are low. (no
change condition )

CM305.52 16
• When the sixteenth clock pulse arrives all the four flip flops
change from 1 to 0.

• so the output is given by Q=0000.

• The counting sequence is completed through a passage of


sixteen clock pulses.

CM305.52 17
Advantages

• Clock pulses are applied simultaneously to all the flip flops.

• Propagation delay is less.

• Speed of operation is more.

• Requires minimum number of gates.

• Cost is somewhat low compared to asynchronous counter.

CM305.52 18
Summary

• In synchronous counter all flip-flops change its output in


synchronous with clock

• Synchronous counter is faster than asynchronous


counter.

• In synchronous counter all the flip flops one triggered by


the same clock

• In asynchronous counter each flip-flop is triggered by the


o/p of previous flip- flop.

CM305.52 19
QUIZ

1. In synchronous counter clock pulses are applied in a


manner of

a) at a time

b) output of 1st flip-flop as clock to the next

c) depending on the no.of flip-flops

d) none

CM305.52 20
2. The no .of flip-flops required for Mod-16 counter are

a) 2

b) 3

c) 4

d) 16
CM305.52 21
3. Among these which counter has high speed of operation

a) ripple counter

b) Mod 16 counter

c) decade counter

d) none

CM305.52 22
4. If J=1,K=1 the output of the flip flop is

a) 1

b) 0

c) toggle

d) none

CM305.52 23
EXPECTED QUESTIONS

1. Explain the principle of operation of 4-Bit synchronous


counter ?

3. What are the advantages of synchronous counter ?

3. Draw the timing diagram of synchronous counter ?

CM305.52 24
Assignment

1. Draw the logic circuit of 4- bit synchronous counter

2. Compare the timing diagrams of synchronous counter


with ripple counter.

CM305.52 25

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