Noida Institute of Engineering and Technology, Greater

Noida

Control Unit

Unit: 3

Computer Organization &

Swarnima
Architecture
CSE
B Tech 3rd Sem Department

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1
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 Content

Control Unit:
Instruction types, formats
Instruction cycles and sub cycles (fetch and execute etc)
Micro operations
Execution of a complete instruction.
Program Control
Reduced Instruction Set Computer
Pipelining
Hardwire and micro programmed control
Micro programmed sequencing
Concept of horizontal and vertical microprogramming.

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 Course Objective

• Implementation of control unit techniques and the concept of

Pipelining.
• Study of Instruction, types of instruction, format of instuction,Cycle
and sub cycle, micro operation.

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 Course Outcome

• Implementation of control unit techniques and the concept of

Pipelining.

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 CO-PO Mapping

COMPUTER ORGANIZATION AND ARCHITECTURE

(KCS-302)

CO.K PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12

KCS-
302.3 3 2 2 1 2 2 1 1 2 2 1 2

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 CO- PSO Mapping

COMPUTER ORGANIZATION AND ARCHITECTURE

(KCS-302)
CO.K PSO1 PSO2 PSO3 PSO4
KCS-302.2 3 3 3 2

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 Prerequisite and Recap

• Arithmetic Logic Unit

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 Instruction

• Program
– A sequence of (machine) instructions
• (Machine) Instruction
– A group of bits that tell the computer to perform a specific
operation (a sequence of micro-operation)
• The instructions of a program, along with any needed data are
stored in memory
• The CPU reads the next instruction from memory
• It is placed in an Instruction Register (IR)
• Control circuitry in control unit then translates the instruction into
the sequence of micro operations necessary to implement it
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 Instruction Types
• Functional / Data Processing Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
• Transfer Instructions
- Data transfers between the main memory and the processor registers

- LDA, STA
• Control Instructions
- Program sequencing and control
- HALT, NOP, RESET
• Input / Output Instructions
- Input and output
- INP, OUT

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 Instruction Types

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 Instruction Types

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 Instruction Types

Most computer instructions can be classified into three categories:

1. Data transfer instructions
2. Data manipulation instructions
3. Program control instructions

•Data transfer instructions cause transfer of data from one location to

another without changing the binary information content.
•Data manipulation instructions are those that perform arithmetic,
logic, and shift operations.
•Program control instructions provide decision-making capabilities and
change the path taken by the program when executed in the
computer.

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 Instruction Types
1.Data Transfer Instructions -
Data transfer instructions move data from one place in the computer
to another without changing the data content.

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 Instruction Types

• Load instruction has been used mostly to designate a transfer from

memory to a processor register, usually an accumulator.
• Store instruction designates a transfer from a processor register into
memory.
• Move instruction has been used in computers with multiple CPU
registers to designate a transfer from one register to another.
• Exchange instruction swaps information between two registers or a
register and a memory word.
• Input and output instructions transfer data among processor
registers and input or output terminals.
• Push and Pop instructions transfer data between processor registers
and a memory stack.

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 Instruction Types

ADR stands for an address, NBR is a number or operand, X is an

index register, R1 is a processor register, and AC is the accumulator
register
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 Instruction Types

2. Data Manipulation Instructions -

Data manipulation instructions perform operations on data and
provide the computational capabilities for the computer. The data
manipulation instructions in a typical computer are usually divided
into three basic types:
A.Arithmetic instructions
B. Logical and bit manipulation instructions
C.Shift instructions

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 Instruction Types

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 Instruction Types

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 Instruction Types

3. Program control instructions –

•Program control instructions specify conditions for altering the content
of the program counter, while data transfer and manipulation
instructions specify conditions for data-processing operations.
•The change in value of the program counter as a result of the execution
of a program control instruction causes a break in the sequence of
instruction execution.

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 Instruction Types

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 Instruction Types
Status Bit Conditions

•It is sometimes convenient to supplement the ALU circuit in the CPU

with a status register where status bit conditions can be stored for
further analysis.
•Status bits are also called condition-code bits or flag bits.

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 Instruction Types

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 Instruction Types
Status Bit Conditions
1.Bit C (carry) is set to 1 if the end carry C8 is 1. It is cleared to 0 if the
carry is 0.
2.Bit S (sign) is set to 1 if the highest-order bit F7 is 1. It is set to 0 if the
bit is 0.
3.Bit Z (zero) is set to 1 if the output of the ALU contains all 0’s. It is
cleared to 0 otherwise. In other words, Z 1 if the output is zero and Z 0
if the output is not zero.
4.Bit V (overflow) is set to 1 if the exclusive-OR of the last two carries is
equal to 1, and cleared to 0 otherwise. This is the condition for an
overflow when negative numbers are in 2’s complement

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 Instruction Types
Conditional Branch Instructions

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 Instruction Format
• In the Basic Computer, bit 15 of the instruction specifies the
addressing mode (0: direct addressing, 1: indirect addressing)

• Since the memory words, and hence the instructions, are 16 bits long,
that leaves 3 bits for the instruction’s opcode

Instruction Format

15 14 12 11 0

I Opcode Address

Addressing
mode

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 Instruction Format

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 Instruction Format

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 Instruction Format

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 Instruction Format

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 Instruction Cycle & Sub Cycle

• In Basic Computer, a machine instruction is executed in the

following cycle:
– Fetch an instruction from memory
– Decode the instruction
– Read the effective address from memory if the instruction has
an indirect address
– Execute the instruction

• After an instruction is executed, the cycle starts again at step 1,

for the next instruction
• Note: Every different processor has its own (different)
instruction cycle

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 Fetch and Decode

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 Fetch and Decode

T0 Cycle:
1.Place the content of PC onto the bus by making the bus selection
inputs S2S1S0 equal to 010.
2.Transfer the content of bus to AR by enabling the LD input of AR.
T1 Cycle:
1.Enable the read input of memory.
2.Place the content of memory onto the bus by making S2S1S0=
111.
3.Transfer the content of bus to IR by enabling the LD input of IR.
4.Increment PC by enabling the INR input of PC.

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 Instruction Cycle & Sub Cycle
Instruction Cycle

There are typically three stages of an instruction cycle that the CPU carries
out:
•Fetch the instruction from memory. This step brings the instruction into
the instruction register, a circuit that holds the instruction so that it can be
decoded and executed.
•Decode the instruction.
•Read the effective address from memory if the instruction has an indirect
address.
•Execute the instruction.

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 Instruction Cycle & Sub Cycle

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 Execution of Complete Instruction

FETCH

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 Execution of Complete Instruction

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 Micro operations
The operations performed on the data stored in registers known as
micro-operations. Example: Shift, Count Clear and Load. The micro-
operations are classified as follows.
1. Register transfer micro-operations: These type of micro
operations are used to transfer from one register to another binary
information.

2. Arithmetic micro-operations : These micro-operations are

used to perform on numeric data stored in the registers some
arithmetic operations.

3. Logic micro-operations: These micro operations are used to

perform bit style operations / manipulations on non numeric data.

4.Shift micro operations: As their name suggests they are used

to perform shift operations in data store in registers.
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 Micro operations
1. Register transfer micro-operations: These type of micro operations
are used to transfer from one register to another binary
information.
2. Designate information transfer from one register to another by
R2 ← R1
If the transfer is to occur only under a predetermined control
condition, designate it by If (P = 1) then (R2 ← R1) or, P: R2 ← R1,
where P is a control function that can be either 0 or 1

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 Micro operations
Arithmetic Micro operations
Example Description
R3 ← R1 + R2 Addition
R3 ← R1 - R2 (R1 + R2' + 1) Subtraction
Complement (really a logic
R2 ← R2'
operation)
R2 ← -R2 (R2' + 1) Negation
R1 ← R1 + 1 Increment
R1 ← R1 - 1 Decrement

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 Micro operations
Logic Micro operations

Logic Micro-Operations: individual bits of registers are operated with

other corresponding register bits. Example: the XOR of R2 and R1 is
symbolized by
P: R1 ←R1 ⊕R2
Example: R1 = 1010 and R2 = 1100
1010
Content of R1
1100
Content of R2
0110
Content of R1 after P = 1

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 Micro operations
Shift Micro operations

Shift Micro-Operations: – these operations are used for serial transfer of

data. They are also used in conjunction with arithmetic, logic, and other
data-processing operation.
The content of register can be shifted to the left or to the right. At the
same time the bits are shifted, the flip flop receives the binary
information from the serial input.
There are three types of shift micro operation-
1. Logic shift 2. Circular shift 3. Arithmetic shift

Logical Shift:- The symbol “shl” is used for logical shift left
and “shr” is used for logical shift right.

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 Micro operations

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 Micro operations

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 Micro operations

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 Program Control
•Program control is how a program makes decisions or organizes its
activities. Program control typically involves executing particular code
based on the outcome of a prior operation or a user input.

•Program control is how a program makes decisions or organizes its

activities. Program control typically involves executing particular code
based on the outcome of a prior operation or a user input.

•A program control instruction changes address value in the PC and hence

the normal flow of execution.

•Change in PC causes a break in the execution of instructions. capability to

branch to different program segments. Branch (BR) and Jump (JMP)
instructions are used sometimes interchangeably but, they are different.

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 Program Control

Bit C= 1- carry gen

Bit S= 1- neg number
Bit Z-1- output is zero
Bit V= 1- overflow occured

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 Program Control

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 Program Control
Types of Program Control Instructions:
There are different types of Program Control Instructions:
1.Compare Instruction:
Compare instruction is specifically provided, which is similar to a subtract
instruction except the result is not stored anywhere, but flags are set
according to the result.
Example: CMP R1, R2 ;

2. Unconditional Branch Instruction:

It causes an unconditional change of execution sequence to a new location.
Example: JUMP L2

3. Conditional Branch Instruction:

A conditional branch instruction is used to examine the values stored in the
condition code register to determine whether the specific condition exists
and to branch if it does.
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 Program Control
Example: Assembly Code : BE R1, R2, L1
Compiler allocates R1 for x and R2 for y
High Level Code: if (x==y) goto L1;
4. Subroutines:
A subroutine is a program fragment that lives in user space,
performs a well-defined task. It is invoked by another user program
and returns control to the calling program when finished.
Example: CALL and RET
5. Halting Instructions:
NOP Instruction – NOP is no operation. It cause no change in the
processor state other than an advancement of the program
counter. It can be used to synchronize timing.
HALT – It brings the processor to an orderly halt, remaining in an
idle state until restarted by interrupt, trace, reset or external
action.
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 Program Control
6. Interrupt Instructions:

Interrupt is a mechanism by which an I/O or an instruction can

suspend the normal execution of processor and get itself serviced.

RESET – It reset the processor. This may include any or all setting
registers to an initial value or setting program counter to standard
starting location.

TRAP – It is non-maskable edge and level triggered interrupt. TRAP

has the highest priority and vectored interrupt.

INTR – It is level triggered and maskable interrupt. It has the lowest

priority. It can be disabled by resetting the processor.

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 Reduced Instruction Set Computer
RISC is a microprocessor that is designed to perform a smaller
number of types of computer instructions so that it can operate at
a higher speed (MIPS).

Since each instruction type that a computer must perform

requires additional transistors and circuitry.

A larger list or set of computer instructions tends to make the

microprocessor more complicated and slower in operation.

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 Reduced Instruction Set Computer
Characteristic of RISC –
•Simpler instruction, hence simple
instruction decoding.

•Instruction come under size of one word.

•Instruction take single clock cycle to get

executed.

•More number of general purpose

register.

•Simple Addressing Modes.

•Less Data types.
•Pipeline can be achieved.
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 Complex Instruction Set Computing
 It is a CPU design plan based on single commands, which are
skilled in executing multi-step operations.

A complex instruction set computer is a computer where single

instructions can perform numerous low-level operations like a load
from memory, an arithmetic operation, and a memory store”.

CISC has the capacity to perform multi-step operations or

addressing modes within one instruction set. It is the CPU design
where one instruction works several low-level acts.

The CISC approach attempts to minimize the number of

instructions per program but at the cost of increase in number of
cycles per instruction.

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 Complex Instruction Set Computer
Characteristic of CISC

•Complex instruction, hence complex

instruction decoding.

•Instruction are larger than one word size.

•Instruction may take more than single clock

cycle to get executed.

•Less number of general purpose register as

operation get performed in memory itself.

•Complex Addressing Modes.

•More Data types.
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 CISC Vs. RISC

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 Pipelining
Pipelining is a technique where multiple instructions are overlapped
during execution.

Pipelining is the process of accumulating instruction from the

processor through a pipeline.

It allows storing and executing instructions in an orderly process. It is

also known as pipeline processing.

Pipelining is a process of arrangement of hardware elements of the

CPU such that its overall performance is increased.

Simultaneous execution of more than one instruction takes place in a

pipelined processor.

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 Pipelining

Pipeline Stages
RISC processor has 5 stage instruction pipeline to execute all the
instructions in the RISC instruction set.
Stage 1 (Instruction Fetch)
In this stage the CPU reads instructions from the address in the memory
whose value is present in the program counter.

Stage 2 (Instruction Decode)

In this stage, instruction is decoded and the register file is accessed to get
the values from the registers used in the instruction.

Stage 3 (Instruction Execute)

In this stage, ALU operations are performed.

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 Pipelining
Stage 4 (Memory Access)
In this stage, memory operands are read and written from/to the
memory that is present in the instruction.

Stage 5 (Write Back)

In this stage, computed/fetched value is written back to the register
present in the instructions.

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 Pipelining

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 Arithmetic Pipelining
 Arithmetic Pipelines are commonly used in various high-performance computers.

 They are used in order to implement floating-point operations, fixed-point

multiplication, and other similar kinds of calculations that come up in scientific
situations.

 Let’s look at an example to better understand the ideas of an arithmetic pipeline.

We perform addition and subtraction of floating points on a unit of the pipeline
here.

The inputs in the floating-point adder pipeline refer to two different normalized
floating-point binary numbers. These are defined as follows:
A = X * 2x = 0.9504 * 103
B = Y * 2y = 0.8200 * 102
Where x and y refer to the exponents and X and Y refer to two fractions representing
the mantissa.

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 Arithmetic Pipelining
 The floating-point addition and subtraction process is broken into four pieces.

 The matching sub-operation to be executed in the specified pipeline is contained in

each segment.

 The four segments depict the following sub-operations:

1. Comparing the exponents using subtraction

2. Aligning the mantissa
3. Adding or subtracting the mantissa
4. Normalizing the result

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 Arithmetic Pipelining
 The floating-point addition and subtraction process is broken into four pieces.

 The matching sub-operation to be executed in the specified pipeline is contained in

each segment.

 The four segments depict the following sub-operations:

1. Comparing the exponents using subtraction

2. Aligning the mantissa
3. Adding or subtracting the mantissa
4. Normalizing the result

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 Arithmetic Pipelining
 The floating-point addition and subtraction process is broken into four pieces.

 The matching sub-operation to be executed in the specified pipeline is contained in

each segment.

 The four segments depict the following sub-operations:

1. Comparing the exponents using subtraction

2. Aligning the mantissa
3. Adding or subtracting the mantissa
4. Normalizing the result

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 Arithmetic Pipelining

1. Comparing Exponents by Subtraction

 The difference between the exponents is calculated by subtracting them. The

result’s exponent is chosen to be the larger exponent.
 The exponent difference, 3 – 2 = 1, defines the total number of times the mantissa
associated with the lesser exponent should be shifted to the right.

2. Aligning the Mantissa

 As per the difference of exponents calculated in segment one, the mantissa

corresponding with the smaller exponent would be moved.

A = 0.9504 * 103
B = 0.08200 * 103

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 Arithmetic Pipelining

3. Adding the Mantissa

Both the mantissa would be added in the third segment.

C = A + B = 1.0324 * 103

4. Normalizing the Result

After the process of normalization, the result would be written as follows:

C = 0.1324 * 104

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 Instruction Pipelining
 Pipeline processing can happen not only in the data stream but also in the
instruction stream.

 To perform tasks such as fetching, decoding and execution of instructions, most

digital computers with complicated instructions would require an instruction
pipeline.

 In general, each and every instruction must be processed by the computer in the
following order:

1. Fetching the instruction from memory

2. Decoding the obtained instruction
3. Calculating the effective address
4. Fetching the operands from the given memory
5. Execution of the instruction
6. Storing the result in a proper place

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 Instruction Pipelining
 Each step is carried out in its own segment, and various segments may take
different amounts of time to process the incoming data.

 Furthermore, there are occasions when multiple segments request memory access
at the very same time, requiring one segment to wait unless and until the memory
access of another is completed.

 If the instruction cycle is separated into equal-length segments, the organization of

an instruction pipeline will become much more efficient.

 A four-segment type of instruction pipeline refers to one of the most common

instances of this style of organization.

 A four-segment instruction pipeline unifies two or more distinct segments into a

single unit. For example, the decoding of the instruction and the calculation of the
effective address can be merged into a single segment.

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 Instruction Pipelining

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 Instruction Pipelining
 A four-segment instruction pipeline is illustrated in the block diagram given above.
The instructional cycle is divided into four parts:

 Segment 1
 The implementation of the instruction fetch segment can be done using the FIFO or
first-in, first-out buffer.

 Segment 2
 In the second segment, the memory instruction is decoded, and the effective
address is then determined in a separate arithmetic circuit.

 Segment 3
 In the third segment, some operands would be fetched from memory.

 Segment 4
 The instructions would finally be executed in the very last segment of a pipeline
organisation.

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 Control Unit (CU)
Control unit (CU) of a processor translates from machine instructions
to the control signals for the microoperations that implement them
Control units are implemented in one of two ways
Hardwired Control
CU is made up of sequential and combinational circuits to
generate the control signals
Microprogrammed Control
A control memory on the processor contains microprograms that
activate the necessary control signals

We will consider a hardwired implementation of the control unit for

the Basic Computer

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 Control Unit (CU)
•Control Unit is the part of the computer’s central processing unit
(CPU), which directs the operation of the processor.
•It is the responsibility of the Control Unit to tell the computer’s
memory, arithmetic/logic unit and input and output devices how to
respond to the instructions that have been sent to the processor.
•A control unit works by receiving input information to which it
converts into control signals, which are then sent to the central
processor.

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 Functions of the Control Unit
It coordinates the sequence of data movements into, out of, and
between a processor’s many sub-units.
It interprets instructions.
It controls data flow inside the processor.
It receives external instructions or commands to which it converts to
sequence of control signals.
It controls many execution units(i.e. ALU, data buffers and registers)
contained within a CPU.
It also handles multiple tasks, such as fetching, decoding, execution
handling and storing results.

Types of the Control Unit

There are two types of control units:
Hardwired control unit and
Micro programmable control unit.
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 Control Unit (CU)

•Control unit of Basic Computer

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 Control Unit (CU)

•HARDWIRED/MICROPROGRAMMED

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 Hardwired control unit
It In the hardwired organization, the control logic is implemented
with gates, flip-flops, decoders, and other digital circuits. It has the
advantage that it can be optimized to produce a fast mode of
operation.
A hardwired control, as the name implies, re­ quires changes in the
wiring among the various components if the design has to be modified
or changed.

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 Microprogrammed control unit
It In the microprogrammed organization, the control information is
stored in a control memory.
The control memory is programmed to initiate the required
sequence of microoperations.
In the microprogrammed control, any required changes or
modifications can be done by updating the microprogram in control
memory.

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 Hardwired/Microprogrammed

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 Concept of horizontal and vertical
microprogramming.
Micro-programmed control unit
Micro-programmed control unit can be classified into two types based
on the type of Control Word stored in the Control Memory.
• Horizontal micro-programmed control unit
• Vertical micro-programmed control unit.

Horizontal micro-programmed control unit, the control signals are

represented in the decoded binary format, i.e., 1 bit/CS. Here ‘n’
control signals require n bit encoding.
•In horizontal organization, as mentioned above, you can assume that
every bit in the control word corresponds to a control signal.
•Horizontal organization has more control over the potential
parallelism of operations in the data path; however, it uses up lots of
control store.
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 Concept of horizontal and vertical
microprogramming.
Vertical micro-programmed control unit, the control signals are
represented in the encoded binary format. Here ‘n’ control signals
require log2n bit encoding.

•In the case of a vertical organization, the signals are grouped and
encoded in order to reduce the size of the control word.

•Vertical organization, on the other hand, is easier to program, not very

different from programming a RISC machine in assembly language, but
needs extra level of decoding and may slow the machine down.

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 Concept of horizontal and vertical
microprogramming.

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 Flynn’s Classification

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 Flynn’s Classification

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 Flynn’s Classification

Single-instruction, single-data (SISD) systems –


An SISD computing system is a uniprocessor machine which is capable of executing a
single instruction, operating on a single data stream.

In SISD, machine instructions are processed in a sequential manner and computers
adopting this model are popularly called sequential computers.

Most conventional computers have SISD architecture. All the instructions and data to
be processed have to be stored in primary memory.
The speed of the processing element in the SISD model is limited(dependent) by the
rate at which the computer can transfer information internally.

Dominant representative SISD systems are IBM PC, workstations.

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 Flynn’s Classification

Single-instruction, multiple-data (SIMD) systems –


An SIMD system is a multiprocessor machine capable of executing the same instruction
on all the CPUs but operating on different data streams.
Machines based on an SIMD model are well suited to scientific computing since they
involve lots of vector and matrix operations.
So that the information can be passed to all the processing elements (PEs) organized
data elements of vectors can be divided into multiple sets(N-sets for N PE systems) and
each PE can process one data set.
Dominant representative SIMD systems is Cray’s vector processing machine.

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 Flynn’s Classification

Multiple-instruction, single-data (MISD) systems –


An MISD computing system is a multiprocessor machine capable of executing different
instructions on different PEs but all of them operating on the same dataset .

The system performs different operations on the same data set. Machines built using the
MISD model are not useful in most of the application, a few machines are built, but none
of them are available commercially.

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 Flynn’s Classification

Multiple-instruction, multiple-data (MIMD) systems –


An MIMD system is a multiprocessor machine which is capable of executing multiple
instructions on multiple data sets.
Each PE in the MIMD model has separate instruction and data streams; therefore
machines built using this model are capable to any kind of application.
Unlike SIMD and MISD machines, PEs in MIMD machines work asynchronously.

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 Flynn’s Classification

Multiple-instruction, multiple-data (MIMD) systems –


An MIMD system is a multiprocessor machine which is capable of executing multiple
instructions on multiple data sets.
Each PE in the MIMD model has separate instruction and data streams; therefore
machines built using this model are capable to any kind of application.
Unlike SIMD and MISD machines, PEs in MIMD machines work asynchronously.

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 Flynn’s Classification

 MIMD machines are broadly categorized into shared-memory

MIMD and distributed-memory MIMD based on the way PEs are coupled to the
main memory.

 In the shared memory MIMD model (tightly coupled multiprocessor systems), all
the PEs are connected to a single global memory and they all have access to it.
 The communication between PEs in this model takes place through the shared
memory, modification of the data stored in the global memory by one PE is visible to
all other PEs.
 Dominant representative shared memory MIMD systems are Silicon Graphics
machines and Sun/IBM’s SMP (Symmetric Multi-Processing).

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 Flynn’s Classification

 MIMD machines are broadly categorized into shared-memory

MIMD and distributed-memory MIMD based on the way PEs are coupled to the
main memory.

 In the shared memory MIMD model (tightly coupled multiprocessor systems), all
the PEs are connected to a single global memory and they all have access to it.
 The communication between PEs in this model takes place through the shared
memory, modification of the data stored in the global memory by one PE is visible to
all other PEs.
 Dominant representative shared memory MIMD systems are Silicon Graphics
machines and Sun/IBM’s SMP (Symmetric Multi-Processing).
 In Distributed memory MIMD machines (loosely coupled multiprocessor systems)
all PEs have a local memory.
 The communication between PEs in this model takes place through the
interconnection network (the inter process communication channel, or IPC).
 The network connecting PEs can be configured to tree, mesh or in accordance with
the requirement.

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 Flynn’s Classification

 The shared-memory MIMD architecture is easier to program but is less tolerant to

failures and harder to extend with respect to the distributed memory MIMD model.
 Failures in a shared-memory MIMD affect the entire system, whereas this is not the
case of the distributed model, in which each of the PEs can be easily isolated.
 Moreover, shared memory MIMD architectures are less likely to scale because the
addition of more PEs leads to memory contention.
 This is a situation that does not happen in the case of distributed memory, in which
each PE has its own memory.
 As a result of practical outcomes and user’s requirement , distributed memory MIMD
architecture is superior to the other existing models.

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 Faculty Video Links, You tube Courses Details

You tube/other Video Links

• https://www.youtube.com/watch?v=vcvgvqnH7GA
• https://www.youtube.com/watch?v=U62iP8RkZIk
• https://www.youtube.com/watch?v=8b1Cs1Uf6hI
• https://www.youtube.com/watch?v=MSac_s-W0pc
• https://www.youtube.com/watch?v=sJdCD_APVq8
• https://www.youtube.com/watch?v=_EKgwOAAWZA

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 Daily Quiz

• Sketch Instruction cycle and sub cycle

• Write down the main function of control unit
• Perform ashl and ashr for given CSE code 10.
• Define pipelining with example.
• Perform shift micro operation on 1100101 .

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 Weekly Assignment

 Define micro operation, microinstruction, micro program,

microcode.

 List the characteristics of RISC and CISC.

 Differentiate between horizontal and vertical

microprogramming.

 Differentiate between hardwired control and micro programmed

control.

 Explain phases of Instruction cycle.

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 MCQ

• 1. 1. The decoded instruction is stored in ______

a) IR b) PC c) Registers d) MDR
2. Which registers can interact with the secondary storage?
a) MAR b) PC c) IR d) R0
3. During the execution of a program which gets initialized first ?
a) MDR b) IR c) PC d) MAR
4. _______ is used to store data in registers.
a) D flip flop b) JK flip flop c) RS flip flop d) None of the mentioned
5. Write the phases of Instruction--------------------------------
6 Perform cil and cir on given data 1001.
7. Write full form of RISC and CISC---------------------------------------------
Solution 1 a. 2a. 3 c. 4 a

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 Old Question Papers

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 Old Question Papers

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 Expected Questions for University Exam

 Write a program to evaluate the arithmetic expression by using

Three, Two, One and Zero address instruction. X = (A+B*C) /
(D+E*F/G+H).
Differentiate between RISC & CISC based microprocessor.
What is micro programmed control unit? Give the basic structure of
micro programmed control unit.
How pipeline performance can be measured? Discuss. Give a space
time diagram for visualizing the pipeline behavior for a four stage
pipeline.
Perform Shift micro operation for given data 11001010.

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 Summary

In previous slides we discuss in details

Control Unit:
Instruction types, formats
Instruction cycles and sub cycles (fetch and execute etc)
Micro operations
Execution of a complete instruction.
Program Control
Reduced Instruction Set Computer
Pipelining
Hardwire and micro programmed control
Micro programmed sequencing
Concept of horizontal and vertical microprogramming.

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