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Pass Transistor Logic

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13 views

Pass Transistor Logic

Uploaded by

Shiva
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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ST.

ANN’S COLLEGE OF ENGINEERING &


TECHNOLOGY :: CHIRALA
VLSI DESIGN

CMOS Combinational and Sequential Logic


circuit Design - Static CMOS Design
(UNIT-IV)

PRESENTED BY

Dr.D.RAJENDRA PRASAD
Professor & In-charge HOD
Department of ECE
OUTLINE

 Complementary CMOS

 Rationed Logic

 Pass - Transistor Logic


Static Properties of Complementary CMOS Logic
Gates
 They exhibit rail to rail swing with VOH = VDD and VOL= GND.

 The circuit has no static power dissipation, since the circuits


are designed such as pull up pull down networks are mutually
exclusive

 The Analysis of DC voltage transfer characteristics and the


noise margin is more complicated than for the inverter as these
parameters depends on the input data pattern applied to the
gate.
Rationed Logic
 Although, the static CMOS logic style is highly robust and scalable
with technology but it requires 2N transistors in implementation
of an N-input logic gates.
 Also, the load capacitance is significant since each gate drives
two transistors (a PMOS and an NMOS) per fan-out.

 Rationed logic is an alternate method to reduce the number of


transistors required to implement a given logic function, at the
cost of reduced robustness and extra power dissipation.
 It is one method to reduce the circuit complexity of static CMOS.

 Here, the logic function is built in the PDN and used in


combination with a simple load device (PUN).
Rationed Logic
Rationed Logic
 The need of the PUN in complementary CMOS is to provide a
conditional path between VDD and the output, when the PDN is
turned off.
 In rationed logic, the entire PUN is replaced with a single load
device that pulls up the output when the PDN is turned off.
 Rationed logic, which uses a grounded PMOS load and referred to
as a pseudo-NMOS style. Instead of a combination of active pull-
down and pull-up networks, such a gate consists of an NMOS
pull-down network that realizes the logic function, and a simple
load device.
 This has resulted in a wide variety of possible load configurations
such as Simple resistor, Depletion load and Pseudo-NMOS
Rationed Logic
 The need of the PUN in complementary CMOS is to provide a
conditional path between VDD and the output, when the PDN is
turned off.
 In rationed logic, the entire PUN is replaced with a single load
device that pulls up the output when the PDN is turned off.
 Rationed logic, which uses a grounded PMOS load and referred
to as a pseudo-NMOS style.
 Instead of a combination of active pull-down and pull-up
networks, such a gate consists of an NMOS pull-down network
that realizes the logic function, and a simple load device.
 This has resulted in a wide variety of possible load
configurations such as simple resistor, Depletion load and
Pseudo-NMOS
PASS transistor logic (PTL)
 PASS transistors are used to reduce the layout complexity of
logic circuits
 Pass transistors connected to pass a first and second input
function to an output node in response to selected CONTROL
signals, thereby to generate a selected output function on the
output node.
 The PASS transistor comprises a transistor capable of passing
an input function in response to a CONTROL signal applied to
the transistor thereby to generate an output function related
to the input function.
PASS transistor logic (PTL)
 In general,
 The input function comprises less than all of a set of input
variables &
 The CONTROL function comprises one or more of the
remainder of the set of input variables.
 It is a good alternate to complementary CMOS circuits.
 This family tries to reduce the number of transistors required
by allowing the primary input to drive gate terminals as well
as source drain terminals.
 The main advantage is the reduced number of transistors and
no static power consumption
PASS transistor logic (PTL)
PASS transistor logic AND gate

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