CHAPTER-4

INTRODUCTION TO DIGITAL
SYSTEM DESIGN
PLDs, CPLD,FPGA and ASICs
Architectures

3-1
Outline

 Introduction
 Simple Programmable Logic Designs (SPLDs)
 PLA
 PAL
 Complex Programmable Logic Designs (CPLDs)
 Field-Programmable Gate Array (FPGAs)
 Logic Blocks
 Programmable Routing Switches
 I/O Pads
 Commercial FPGA Products
 Application Specific Integrated Circuits (ASICs)

2
 Introduction: Digital System Design

 To design digital systems there are three options:

 Microprocessors and DSP [software-based]
 Fetch & execute software instructions (e.g., running a word processing
program)
 Very efficient
 Slow &for complex
Power sequential math-intensive tasks
hungry
 Programmable Logic devices (PLDs) [Hardware-based]
 Directly implements logic functions on hardware
Course  Faster
Focus  Less power consumption
 Application Specific Integrated Circuit (ASIC) [Hardware-Based]
 Fastest
 Lowest power consumption
 Introduction: Digital System Design

 DSP [software-based]
 Easy to program (usually standard C)
 Very efficient for complex sequential math-intensive tasks
 Fixed data path-width. Ex: 24-bit adder, is not efficient for 5-bit
addition
 Limited resources

 FPGA & ASIC [Hardware-based]

 Requires HDL language programming
 Efficient for highly parallel applications
 Efficient for bit-level operations
 Large number of gates and resources
 Does not support floating point, must construct your own
3-5
 Introduction: Digital System Design

I. Conventional Approach:
 Board-based designs
 Large # of chips (containing basic logic gates) on a single Printed Circuit
Board (PCB) VDD

PCB Board
7404

7408 7432

X1

X2
X3 Out
Introduction: Digital System Design

II. High-density Single Chip

 A single chip replaces the whole multi-chip design on
PCB
 Programmable Logic Designs (PLDs) or
 Application Specific Integrated Circuits (ASICs)
 Lower overall cost
 On-chip interconnects are many times faster than off-chip wires
 Lower area with the same functionality
 Lower power consumption
 Lower noise
 Definitions

 Field Programmable Device (FPD):

— a general term that refers to any type of integrated

circuit used for implementing digital hardware, where
the chip can be configured by the end user to realize
different designs.
—Programming of such a device often involves placing
the chip into a special programming unit, but some
chips can also be configured “in-system”. Another
name for FPDs is programmable logic devices (PLDs).

3-8
Programmable Logic

• Programmable digital integrated circuit

• Standard off-the-shelf parts
• Desired functionality is implemented by configuring on-
chip logic blocks and interconnections
• Advantages (compared to an ASIC):
• Low development costs
• Short development cycle
• Device can (usually) be reprogrammed
• Types of programmable logic:
• Complex PLDs (CPLD)
• Field programmable Gate Arrays (FPGA)
3-9
Programmable Logic Designs (PLDs)

Digital IC

PLDs ASIC

SPLD CPLD FPGA Semi-Custom Full-Custom

PLA PAL Standard cell Gate Array

This course
 PLD
• The first PLDs were Programmable Logic Arrays (PLAs).
• A PLA is a combinational, 2-level AND-OR device that can be
programmed to realise any sum-of-products logic expression.
• A PLA is limited by:
• the number of inputs (n)
• the number of outputs (m)
• the number of product terms (p)
• We refer to an “n x m PLA with p product terms”. Usually, p << 2 n.
• An n x m PLA with p product terms contains p 2n-input AND gates
and m p-input OR gates.
 PLD • Each input is connected to a buffer that produces a true and a
complemented version of the signal.

A 4x3 PLA with

6 product
terms.

• Potential connections are indicated by Xs.

• The device is programmed by establishing the needed connections.
• The connections are made by fuses.
 PLD
• Compact representation of • O1 = I1·I2 + I1’·I2’·I3’·I4’
the 4x3 PLA with 6 product O2 = I1·I3’ + I1’·I3·I4 + I2
terms. O3 = I1·I2 + I1·I3’ + I1’·I2’·I4’
 PLD
• Another PLD is PAL
(Programmable Array Logic).

• A PAL device has a fixed OR

array.

• In a PAL, product terms are

not shared by the outputs.

• A PAL is usually faster than a

similar PLA.
 PLD
• Part of the logic diagram of the PAL 16L8.

PLD structures are the base to implement many of structures and blocks
shown in next slides
 PLDs
16V8 (20 Pins)

• can have 16 inputs (max) and/or 8 outputs (macrocells)

• has 32 inputs to each of the AND gates (product terms)

22V10 (24 pins)

• can have 22 inputs and/or 10 outputs (max)

• has 44 inputs to each of the AND gates

How about a “128V64” for larger applications?

It will be slower and will more wasted silicon space

Solution? Use CPLDs

Lect #14 Rissacher EE365

 Technology Timeline

The white portions of the timeline bars indicate that although early incarnations of these
technologies may have been available, they weren’t enthusiastically received by the engineers
working in the trenches during this period. For example, although Xilinx introduced the world’s first
FPGA as early as 1984, design engineers didn’t really start using it until the early 1990s.
 Simple Programmable Logic Designs (SPLDs)

 Field Programmable Logic Arrays (FPLA or

x1 x2 x3
PLA)
 Introduced in early 1970s by
Philips
Programmable
connections

 Consists of two levels of logic gates OR plane

P1
 Programmable “wired” AND-plane
 Programmable “wired” OR-plane P2

 Two levels of programmability

 Well-suited for implementing P
3

functions in sum-of-product (SOP)

P
form.
f 1  x1 x2  x1 x3  x1 x2 x3 f 2 4

 x1 x2  x1 x3  x1 x2 x3 AND plane

f1 f2
 SPLD: Programmable Logic Arrays (PLA)

 Each “AND” gate or “OR” gate can have many

inputs
 Wide AND/OR f1  x 1 x 2  x1 x3  x1 x2x 3
gates f xx  x 1 x 3  x1 x 2 x 3
2 1 2
x1 x2 x3 x1 x2 x3

Programmable
connections

OR plane OR plane
Unwanted P1 P1

connections
P2
are “blown” P2

P3
P3

P4

P4

AND plane
AND plane
Short-hand notation f1 f2
f1 f2
 SPLD: PLAs

 Advantages:
 PLA is efficient in terms of its required area for its implementation on IC
 Often used as part of larger chips, e.g., microprocessors

 Drawbacks:
 Two-level programmable logic planes are difficult to fabricate
 Two-level programmable structure introduces significant propagation
delay
 Normally many pins, large package thus, high fabrication cost
To overcome these drawbacks, PAL was introduced
 S P L DP:ro g amr m ba leA ray L o g ic(P
A L )

x1 x2 x3

 PAL:
 Consists of two levels of logic gates
P1
 Programmable “wired” AND-plane
 Fixed OR-gates P2
f1

 Single level of programmability

P3

 Advantages: P4
f2

 Simpler to fabricate
 Better performance AND plane

 Drawbacks: Fixed OR

 Less flexibility
f1  x1x2x3 
x1x2x3
f2  x1x2x3 
 SPLD: Programmable Array Logic (PAL)
 To increase flexibility:
 PALs with various sizes of OR-gates.
 Add extra circuitry to the OR-gate output (Called
“Macrocell”)
To complement Allows Flip-flop Used to connect/disconnet
if needed bypass to the output pin
Each macrocell ~ 20 gates Macrocell Select
Enable

f1

Flip-Flop D Q
0/1

For implementation of circuits that Clk

have multiple stages of logic gates

To AND plane

© M. Shabany, ASIC/FPGA Chip Design

 PLA v.s. PAL

 PLAs are more flexible than PALs since both AND & OR planes are
programmable in PLAs.

 Because both AND & OR planes are programmable, PLAs are expensive
to fabricate and have large propagation delay.

 By using fix OR gates, PALs are cheaper and faster than PLAs.

 Logic expanders increase the flexibilities of PALs, but result in significant

propagation delay.

 PALs usually contain D flip-flops connected to the outputs of OR gates

to implement sequential circuits.

 PLAs and PALs are usually referred to as SPLD.

3-23
 PAL vs. PLA vs. ROM

I3 I2 I1 I I5 I4 I3 I2 I1 I0
Programmable OR array I5 I4 I3 I2 I1 I
0
Fixed OR array Programmable OR array
0

Fixed AND array Programmable AND array

Programmable AND array
O 3O 2O 1O
O 3O 2O 1O
0 O 3O 2O 1 O 0
0

PROM PAL PLA

Indicates programmable connection
Indicates fixed connection
 Commercial SPLD Products
 Commercial SPLD
Products: Manufacturer Product
Altera Classic
Atmel PAL
Lattice ispGAL

 Part number: NN X MM – Example:

S NN: Max # of inputs  22 V 10-
 MM: Max # of outputs (some can be used as 1
inputs)  16 R 8-2
 X=R (outputs are registered by a D-FF)
 X=V (Volatile)
 S: Speed grade
 PAL: 22V10 (Lattice Semiconductors)

 Maximum of 22 inputs Preset

 11 inputs, one clock, 10 in/outs 8

In/Out
Macrocell

 10 inputs/outputs #1

11
 Variable OR gates (8 to 16 Inputs

inputs)
10
Macrocell In/Out
#2

AND
Plane 12
Macrocell In/Out
#3

8
Macrocell In/Out
#10

Clk
 SPLD Scalability

 It is very hard to scale SPLDs for more complex designs

 b/c the structure of the logic planes grow too quickly in size as
the # of inputs increases

 Solution:
 Integrate multiple SPLDs onto a single chip
 Plus internal programmable interconnect to connect them
together

Complex PLDs (CPLD)

CPLD Structure

Integration of several PLD blocks with a programmable

interconnect on a single chip
I/O

I/O
I/O Block

I/O Block
• PLD
PLD PLD
PLD •
Block

Block
• Block •
• Block Block
Block •

Interconnection
Interconnection Matrix
Matrix
I/O

I/O
I/O Block

I/O Block
• PLD
PLD PLD
PLD •
Block

Block
• •
• Block
Block Block
Block •

28
 CPLD

 Consists of 2 to 100 PAL blocks

 Interconnection contains programmable
 switches
The number of switches is PAL

I/O block
block
critical

I/O block
PAL
block
 Commercial
CPLDs:
Manufacturer Product
Altera MAX 7000, MAX 10K
Interconnection wires
Atmel ATF
Xilinx XC9500
AMD Mach series
PAL
ICT PEELArray

I/O block
block
I/O block

PAL
Lattice ispLSI series block
 CPLD: Altera MAX7000

 Comprises:
 Several Logic Array Blocks (LAB), a set of 16 macrocells
 Programmable Interconnect Array (PIA)
 Consists of set of wires that span the entire device
 Makes connections between macrocells and chip’s input/output
 In total pins
consists of 32 to 512
macrocells PIA
LAB LAB
 Four dedicated input pins
 For global clock or FF resets LAB LAB

LAB LAB

Altera MAX 7000

 CPLD

 A CPLD comprises multiple PAL-like blocks on a single

chip with programmable interconnect to connect the
blocks.
 CPLD Architecture
I/O block

I/O block
PAL-like PAL-like
block block

Programmable interconnect
I/O block

I/O block
PAL-like PAL-like
block block

3-31
Complex PLDs

• What is the next step in the evolution of programmable

logic?
•More gates!
• How do we get more gates?
• We could put several PALs on one chip and put an
interconnection matrix between them!!

• This is called a Complex PLD (CPLD).

Cypress Programmable
interconnect matrix.
CPLD

Each logic block is similar to

a 22V10.

Logic block diagram

Cypress CPLDs

•Ultra37000 Family
•32 to 512 Macrocells
•Fast (Tpd 5 to 10ns depending on
number of macrocells)
•Very good routing resources for a
CPLD
A General CPLD structure

A collection of PLDs on a single chip with

Programmble interconnects
 Who makes the CPLDs?

Manufacturer
Manufacturer CPLD
CPLDProducts
Products URL
URL

Altera
Altera MAX
MAX5000,
5000,7000
7000&&9000
9000 www.altera.com
www.altera.com
Altmel
Altmel ATF
ATF&&ATV
ATV www.atmel.com
www.atmel.com
Cypress
Cypress FLASH370, Ultra37000
FLASH370, Ultra37000 www.cypress.com
www.cypress.com
Lattice
Lattice ispLSI
ispLSI1000
1000toto8000
8000 www.latticesemi.com
www.latticesemi.com
Philips
Philips XPLA
XPLA www.philips.com
www.philips.com
Vantis
Vantis MACH
MACH11toto55 www.vantis.com
www.vantis.com
Xilinx
Xilinx XC9500
XC9500 www.xilinx.com
www.xilinx.com

Let’s
Let’stakes
takesaalook
lookatatthis
this

Lect #14 Rissacher EE365

 Altera MAX CPLD

I/O Cell
LAB (Logic Array Block)

LAB LAB
LA
(local

•••
LAB LAB
array)
LAB LAB

Altera MAX chip Macroccell

Chip-wide
interconnect  Each LAB contains 16 macrocells

3-37
 Macrocell of Altera MAX CPLD
System clock System enable

Local Array
Clock, clear, preset, enable
3
Programmable
inversion
M OUT
D Q

5
Product term
select

Parallel expander
To next macrocell

114

Macrocell

MAX 9000 has 33 inputs, can you explain why LA has 114 inputs?
3-38
CPLD: Altera MAX7000

LAB (Logic Array Block)

LA
PIA
LAB LAB

LAB LAB

LAB LAB

Altera MAX
 CPLD: Altera MAX7000

 Comprises:
 Wide programmable AND array followed by
 A narrow fixed OR array

 OR gate can be fed from:

 Any of the five product terms within the macrocell
 or up to 15 extra product terms from other macrocells in the same
LAB more flexibility
C P L D:A M
ltera A X 70 0 0 In terco n n Aect rch itecu re

LAB
column channel row channel

t PIA

LAB2
LAB
1

PIA

t PIA
LAB6

Array-based (MAX 3000, 7000) Mesh-based (MAX 9000, 10K)

 Fixed routing delay b/w blocks  LABs can connect to row and column
 Simple and predictable delay channels
 Not scalable to large # of  Suitable for large # of macrocells (512)
macrocells
 Advanced Micro Devices (AMD) CPLDs:

 Mach family (Mach 1 to Mach 5) all EEPROM-based

technology

 Mach
Mach 1,
3, 2: Multiple
4, 5: Several22V16 PALs 34V16
optimized I/O

 MachPALs
4: I/O 34V16 34V16 34V16 34V16 I/O
 Consists of:
 6 to 16 PAL (2K-5K I/O 34V16 34V16 34V16 34V16 I/O

gates) Central Switch Matrix Clk

 Central switch matrix
 In-circuit I/O 34V16 34V16 34V16 34V16 I/O
programmable
I/O 34V16 34V16 34V16 34V16 I/O

I/O

All connections b/w PALs and even inside a PAL

routed through the central switch matrix
 AMD Mach 4 PAL Block:

 34V16 (34 maximum inputs, volatile, max 16 outputs)

 In addition to a normal PAL, it consists of:
 product term allocator b/w AND plane and macrocells, which
distributes
product terms to whichever OR-gate required
 Output switch matrix b/w OR gates and I/O

Any macrocell can drive

any of the I/O pins
(more flexibility)
 CPLD Applications:

 Circuits that can exploit wide AND/OR gates and do not need
large number of flip-flops
 Graphic controllers
 LAN controllers
 UARTs
 Cache control

 Advantages:
 Easy to re-program even in-system
 Predictability of circuit implementation
 High-speed implementation
 Circuit Size Metric

 Size Metric:
 How many basic gates can be built on the circuit
 Common measure: number of two-input NAND
gates
2,000,000
Device Size Design Type
SPLD ~ 200 gates Small

Equivalent gates
200,000
CPLD ~ 10,000 gates Moderate
FPGA ~ 1,000,000 gates Large 2000

200

SPLDs CPLDs FPGAs

 FPGA

 FPGA: (Field-Programmable Gate Array)

 Pre-fabricated silicon devices that can be electrically programmed to become any
kind of digital circuit or system

 A very large array of programmable logic blocks surrounded by programmable

interconnects

 Contains logic blocks instead of AND/OR planes (multi-level logic of arbitrary

depth)

 Can be programmed by the end-user to implement specific applications

 Capacity up to multi-millions gates

 Clock frequency up to 500MHz

 What is an FPGA?
• Field Programmable Gate Array

• Fully programmable alternative to a customized chip

• Used to implement functions in hardware

• Also called a Reconfigurable Processing Unit (RPU)

 FPGA
 Three ages of
FPGAs
Period Age Comments
1984 - 1991 Invention • Technology is limited, FPGAs are much
smaller than the application problem size
• Design automation is secondary
• Architecture efficiency is key
1991 - 1999 Expansion • FPGA size approaches the problem size
• Ease-of-design becomes critical
2000 - 2007 Accumulation • FPGAs are larger than the typical problem
size
• Logic capacity limited by I/O bandwidth
 FPGA Applications

 Popular applications:

 Prototyping a design before the final fabrication (using single

FPGA)
 Emulation of entire large hardware systems (using multiple FPGAs)
 Configured as custom computing machines
 Using programmable parts to “execute” software rather than
software
compilation on a CPU
 On-site hardware reconfiguration
 Low-cost applications
 DSP, logic emulation, network components, etc…
 FPGA History

 First SRAM-based FPGA by Wahlstorm 1967

 First modern-era FPGA by Xilinx 1984
 64 logic blocks
 58 input/outputs
 Today:
 Four main manufacturers (Altera, Xilinx, Actel,
Lattice)
 Over 300,000 logic blocks
 Over 1100 input/outputs
 FPGA Structure

 FPGAs consists of 3 main I/O Block Programmable

Routing Switches
resources:
1. Logic Blocks
 General logic
blocks
FPGA Logic
Memory
Logic
Multiplier

 Memory blocks Block Block

Fabrics
 Multiplier blocks
Logic Logic
2. Program. Routing Switches
Memory Multiplier
Block Block

 Programmable
horizontal/vertical routing Logic
Block
Memory
Logic
Block
Multiplier

channels
 Connecting blocks together Logic Logic
3. I/O Blocks
Memory Multiplier

and I/O
Block Block

 Connecting the chip to the

outside
 FPGA Categories (Structure)
 There are two main categories of FPGAs in terms of their structure:
 Homogeneous:
 Employs only one type of logic block
 Heterogeneous:
 Employs mixture of different blocks such as dedicated memory/multiplier
 Very efficient for specific functions
 Might go waste if not used!

LB LB LB LB LB ME LB MU

LB LB LB LB LB ME LB MU

LB LB LB LB LB ME LB MU

LB LB LB LB LB ME LB MU

Homogeneous Heterogeneous
 FPGA Categories (Floor Plan)

I/O Blocks

LB ME LB MU

I/O Blocks
LB LB

I/O Blocks
ME MU

Symmetrical Row-Based
Array LB ME LB MU

LB ME LB MU

I/O Blocks

I/O Blocks
I/O Blocks

PLD
PLD PLD PLD
Block

Sea-of-Gates Hierarchical
I/O Blocks

PLD
PLD PLD
Block
I/O Blocks

PLD

I/O Blocks
I/O Blocks
Central Switch Matrix PLD
PLD PLD
PLD

PLD PLD
PLD PLD PLD

I/O Blocks I/O Blocks

 FPGA Categories (Architecture)

 There are three main categories of FPGAs in terms of their architecture:

 Fine-grained: (early stages)
 Logic Block (LB) consists of logic gates plus a register
 Coarse-grained: (more efficient)
 LB consists of logic gates, MUXs
 Multi-bit ALU
 Multi-bit registers
 Platform FPGAs:
 Sophisticated logic blocks
 CPU (PowerPC) to run some functions in software
 PCI bus
 RAM, PLL
 Very fast Gbps transceivers for high-speed serial off-chip
communication
Modern Commercial FPGAs
 Modern Commercial FPGAs

 The concept of coupling microprocessors with FPGAs in heterogeneous

platforms was considerably attractive.

 In this programmable platform, microprocessors implement the

control- dominated aspects of DSP systems and FPGAs implement the
data- dominated aspects.

 With FPGAs, the user is given full freedom to define the architecture
which best suits the application.
 FPGA Categories (Fabrics)

 There are two main categories of FPGAs in terms of their fabrics:

 SRAM-based FPGAs (Xilinx, Altera) [Re-programmable, Re-configurable]
 Using Lookup Tables (LUTs) to implement logic blocks
 Using SRAM-cells to implement programmable switches
 Antifuse-based FPGAs (Actel, Lattice, Xilinx, QuickLogic, Cypress)
[Permanent]
 Using multiplexers (MUXs) to implement logic blocks
 Using antifuses to implement programmable switches
Re-programmable FPGAs Permanent

SRAM-Based Antifuse-Based

LUT-Based SRAM-Based MUX-Based Antifuse-Based

Logic Blocks Switches Logic Blocks Switches
 FPGA Categories (Another View)

FPGAs

Logic Blocks Prog. Switches I/O Blocks

LUT-Based MUX-Based SRAM-Based Antifuse-Based

Switches Switches
 The
TheOR
ORgates
gates

GAL16V8
(review seq_1.ppt)

• Each output is
programmable as
combinational or registered
• Also has programmable
And
AndPlane
Plane
output polarity

XOR
XORgates
gatestoto
make
makeinverting
invertingoror
non-inverting
non-invertingbuffer
buffer
Lect #14 Rissacher EE365
 Classifications of Early Programmable Logic
 PLA — a Programmable Logic Array (PLA) is a relatively
small FPD that contains two levels of logic, an AND-
plane and an OR-plane, where both levels are
programmable
 PAL — a Programmable Array Logic (PAL) is a relatively
small FPD that has a programmable AND-plane
followed by a fixed OR-plane
 SPLD — refers to any type of Simple PLD, usually either a
PLA or PAL
 CPLD — a more Complex PLD that consists of an
arrangement of multiple SPLD-like blocks on a
single chip.
 FPGA — a Field-Programmable Gate Array is an FPD
featuring a general structure that allows very high
logic capacity. 3-60
 PLA
Programmable AND Plane Programmable OR Plane

Programmable Node

Un-programmed

Connect

Disconnect
X Y O1 O2 O3 O4

X XY
Y XY
XY XY
X X Y Y

3-61
 PLA

Programmable AND Plane Programmable OR Plane

YZ

XZ

XYZ

XY

X Y Z XY+YZ ? ?

XZ+XYZ

3-62
 PAL

Programmable AND Plane

Fix OR Plane

X Y O1 O2 O3 O4

3-63
 PAL with Logic Expanders
Programmable AND Plane
Fix OR Plane

Logic expanders

3-64
 FPGAs

• Historically, FPGA architectures and companies began

around the same time as CPLDs
• FPGAs are closer to “programmable ASICs” -- large
emphasis on interconnection routing
• Timing is difficult to predict -- multiple hops vs. the fixed
delay of a CPLD’s switch matrix.
• But more “scalable” to large sizes.
• FPGA programmable logic blocks have only a few
inputs and 1 or 2 flip-flops, but there are a lot more
of them compared to the number of macrocells in a
CPLD.

Lect #14 Rissacher EE365

 FPGA
 FPGA consists of an array of programmable basic logic
cells surrounded by programmable interconnect.

 FPGA Structure

Programmable
Logic cell interconnect

I/O Cell

3-66
 FPGA v.s. CPLD
 Capacitance
SPLDs CPLDs FPGAs
Equivalent gates 0 ~ 200 200 ~ 12,000 1000 ~ 1,000,000

 Applications

CPLDs FPGAs
1. Implement random glue logics or
Replace circuits previously 1. FPGAs can be used in various
implemented by multiple SPLDs applications: prototyping, FPGA-based
2. Circuits that can exploit wide computers, on-site hardware re-
AND/OR gates, and do not need configuration, DSP, logic emulation,
a very large number of flip-flops network components, etc.
are good candidates for
implementation in CPLDs.

3-67
 Problems common to CPLDs and FPGAs

• Pin locking
• Small changes, and certainly large ones, can cause the
fitter to pick a different allocation of I/O blocks and
pinout.
• Locking too early may make the resulting circuit slower or
not fit at all.
• Running out of resources
• Design may “blow up” if it doesn’t all fit on a single
device.
• On-chip interconnect resources are much richer than off-
chip; e.g., barrel-shifter example.
• Larger devices are exponentially more expensive.
Lect #14 Rissacher EE365
Reasons to use an FPGA

• Hardwired logic is very fast

• Can interface to outside world

• Custom hardware/peripherals
• “Glue logic” to custom co/processors

• Can perform bit-level and systolic operations not

suited for traditional CPU/MPU
Look Up Tables
• Combinatorial Logic is stored in 16x1 SRAM Look Up Tables
(LUTs) in a CLB Look Up Table
• Example: 4-bit address
Combinatorial Logic
A B C D Z
A
0 0 0 0 0 (2 4)
B
Z 0 0 0 1 0 2
C
D
0
0
0
0
1
1
0
1
0
1
= 64K !
0 1 0 0 1
 Capacity is limited by number of 0 1 0 1 1
inputs, not complexity . . .
 Choose to use each function 1 1 0 0 0
generator as 4 input logic (LUT) 1 1 0 1 0
or as high speed sync.dual port 1 1 1 0 0
RAM WE 1 1 1 1 1
G4
G3 G
G2 Func.
Gen.
G1
Field Programmable Gate Arrays
The FPGA approach to arrange primitive logic elements (logic cells)
arrange in rows/columns with programmable routing between them.

What constitutes a primitive logic element?

Lots of different choices can be made! Primitive element must be classified as a
“complete logic family”.
• A primitive gate like a NAND gate
• A 2/1 mux (this happens to be a complete logic family)
• A Lookup table (I.e, 16x1 lookup table can implement any 4 input logic
function).
Often combine one of the above with a DFF to form the primitive logic element.
Issues in FPGA Technologies
• Complexity of Logic Element
• How many inputs/outputs for the logic element?

• Does the basic logic element contain a FF? What type?

• Interconnect
• How fast is it? Does it offer ‘high speed’ paths that cross the chip? How many of
these?

• Can I have on-chip tri-state busses?

• How routable is the design? If 95% of the logic elements are used, can I route the
design?

• More routing means more routability, but less room for logic elements
Issues in FPGA Technologies
(cont)
• Macro elements
• Are there SRAM blocks? Is the SRAM dual ported?
• Is there fast adder support (i.e. fast carry chains?)
• Is there fast logic support (i.e. cascade chains)
• What other types of macro blocks are available (fast decoders?
register files? )
• Clock support
• How many global clocks can I have?
• Are there any on-chip Phase Logic Loops (PLLs) or Delay Locked
Loops (DLLs) for clock synchronization, clock multiplication?
Issues in FPGA Technologies (cont)
• What type of IO support do I have?
• TTL, CMOS are a given
• Support for mixed 5V, 3.3v IOs?
• 3.3 v internal, but 5V tolerant inputs?

• Support for new low voltage signaling standards?

• GTL+, GTL (Gunning Tranceiver Logic) - used on Pentium II
• HSTL - High Speed Transceiver Logic
• SSTL - Stub Series-Terminate Logic
• USB - IO used for Universal Serial Bus (differential signaling)
• AGP - IO used for Advanced Graphics Port

• Maximum number of IO? Package types?

• Ball Grid Array (BGA) for high density IO
ASICs

• ASIC - Application Specific Integrated Circuit

• In Integrated Circuit (IC) designed to perform a specific function for a
specific application
• As opposed to a standard, general purpose off-the-shelf part such as a
commercial microprocessor or a 7400 series IC
• Gate equivalent - a unit of size measurement corresponding to a 4
transistor gate equivalent (e.g. a 2 input NOR gate)
• Levels of integration:
• SSI - Small scale integration
• MSI - Medium scale integration
• LSI - Large scale integration
• VLSI - Very large scale integration
• USLI - Ultra large scale integration
• Implementation technology
• TTL
• ECL
• MOS - NMOS, CMOS
An Integrated Circuit

Figure 1.1 A packaged Integrated Circuit (IC)

Types of ASICs

• Full-Custom ASICs
• Standard-Cell–Based ASICs
• Gate-Array–Based ASICs
• Channeled Gate Array
• Channelless Gate Array
• Structured Gate Array
• Programmable Logic Devices
• Field-Programmable Gate Arrays
Full-Custom ASICs

• All mask layers are customized in a full-custom ASIC

• Generally, the designer lays out all cells by hand
• Some automatic placement and routing may be done
• Critical (timing) paths are usually laid out completely by hand
• Full-custom design offers the highest performance and lowest part cost
(smallest die size) for a given design
• The disadvantages of full-custom design include increased design time,
complexity, design expense, and highest risk
• Microprocessors (strategic silicon) were exclusively full-custom, but
designers are increasingly turning to semicustom ASIC techniques in
this area as well
• Other examples of full-custom ICs or ASICs are requirements for high-
voltage (automobile), analog/digital (communications), sensors and
actuators, and memory (DRAM)
 Standard-Cell-Based ASICs
• A cell-based ASIC ( CBIC —“sea-
bick”)
• Standard cells
• Possibly megacells ,
megafunctions , full-custom blocks
, system-level macros( SLMs ),
fixed blocks , cores , or Functional
Standard Blocks ( FSBs )
• All mask layers are customized -
transistors and interconnect
• Automated buffer sizing,
placement and routing
• Custom blocks can be embedded
• Manufacturing lead time is about
eight weeks.
Figure 1.2 A cell-based ASIC (CBIC)
Standard Cell Layout

Figure 1.3 Layout of a standard cell

 Standard Cell ASIC Routing
 A “wall” of standard cells forms a flexible block
 Metal2 may be used in a feedthrough cell to cross over cell rows that use metal1 for
wiring
 Other wiring cells: spacer cells , row-end cells , and power cells

Figure 1.4 Routing the CBIC

Gate-Array-Based ASICs

• In a gate-array-based ASIC, the transistors are predefined on the silicon wafer

• The predefined pattern of transistors is called the base array
• The smallest element that is replicated to make the base array is called the base
or primitive cell
• The top level interconnect between the transistors is defined by the designer in
custom masks - Masked Gate Array (MGA)
• Design is performed by connecting predesigned and characterized logic cells
from a library (macros)
• After validation, automatic placement and routing are typically used to convert
the macro-based design into a layout on the ASIC using primitive cells
• Types of MGAs:
• Channeled Gate Array
• Channelless Gate Array
• Structured Gate Array
 Gate-Array-Based ASICs
 Channeled Gate Array
 Only the interconnect is customized

 The interconnect uses predefined spaces

between rows of base cells

 Manufacturing lead time is between two

days and two weeks

Figure 1.5 Channel gate-array die
 Channelless Gate Array
 There are no predefined areas set aside

for routing - routing is over the top of the

gate-array devices
 Achievable logic density is higher than

for channeled gate arrays

 Manufacturing lead time is between two

days and two weeks

Figure 1.6 Sea-Of-Gates (SOG) array die

 Gate-Array-Based ASICs (cont.)
 Structured Gate Array
 Only the interconnect is customized

 Custom blocks (the same for each

design) can be embedded

 These can be complete blocks such as a
processor or memory array, or
 An array of different base cells better
suited to implementing a specific function
Figure 1.7 Gate array die with embedded block
 Manufacturing lead time is between two
days and two weeks.
 Gate-Array-Based ASICs (cont.)

 Programmable Logic Devices

 No customized mask layers or logic cells
 Fast design turnaround
 A single large block of programmable
interconnect
 Erasable PLD (EPLD)
 Mask-programmed PLD
 A matrix of logic macrocells that usually
consist of programmable array logic
followed by a flip-flop or latch
Figure 1.8 Programmable Logic Device (PLD) die
 Field Programmable Gate Array
 None of the mask layers are customized
 A method for programming the basic logic
cells and the interconnect
 The core is a regular array of programmable
basic logic cells that can implement
combinational as well as sequential logic (flip-
flops)
 A matrix of programmable interconnect
surrounds the basic logic cells
 Programmable I/O cells surround the core
 Design turnaround is a few hours
Figure 1.9 Field-Programmable Gate Array (FPGA) die
 Design Flow

1. Design entry - Using a

hardware description language
( HDL ) or schematic entry
2. Logic synthesis - Produces a
netlist - logic cells and their
connections
3. System partitioning - Divide a
large system into ASIC-sized
pieces
4. Prelayout simulation - Check to
see if the design functions
correctly
5. Floorplanning - Arrange the
blocks of the netlist on the chip
6. Placement - Decide the
locations of cells in a block
7. Routing - Make the connections
between cells and blocks
8. Extraction - Determine the
resistance and capacitance of
the interconnect
9. Postlayout simulation - Check
to see the design still works with
the added loads of the
interconnect
Figure 1.10 ASIC design flow
 Comparisons between ASICs and FPGAs
FPGAs ASICs
1 Reconfigurable circuit. FPGAs can be reconfigured with a different
design. They even have capability to reconfigure a part of chip while Permanent circuitry. Once the application specific circuit is taped-out into
remaining areas of chip are still working! This feature is widely used in silicon, it cannot be changed. The circuit will work same for its complete
accelerated computing in data centers. operating life.

2 Design is specified generally using hardware description languages (HDL) Same as for FPGA. Design is specified using HDL such as Verilog, VHDL etc.
such as VHDL or Verilog.
Very high entry-barrier in terms of cost, learning curve, liaising with
3 Easier entry-barrier. One can get started with FPGA development for as semiconductor foundry etc. Starting ASIC development from scratch can
low as USD $30. cost well into millions of dollars.

4 Not suited for very high-volume mass production. Suited for very high-volume mass production.

5 Less energy efficient, requires more power for same function which ASIC Much more power efficient than FPGAs. Power consumption of ASICs can
can achieve at lower power. be very minutely controlled and optimized.

6 Limited in operating frequency compared to ASIC of similar process ASIC fabricated using the same process node can run at much higher
node. The routing and configurable logic eat up timing margin in FPGAs. frequency than FPGAs since its circuit is optimized for its specific function.

7Analog designs are not possible with FPGAs. Although FPGAs may contain ASICs can have complete analog circuitry, for example WiFi transceiver, on
specific analog hardware such as PLLs, ADC etc, they are not much flexible the same die along with microprocessor cores. This is the advantage which
to create for example RF transceivers. FPGAs lack.

8 FPGAs are highly suited for applications such as Radars, Cell Phone Base ASICs are definitely not suited for application areas where the design
Stations etc where the current design might need to be upgraded to use might need to be upgraded frequently or once-in-a-while.
better algorithm or to a better design. In these applications, the high-cost
It is not recommended to prototype a design using ASICs unless it has been
of FPGAs is not the deciding factor. Instead, programmability is the
absolutely validated. Once the silicon has been taped out, almost nothing
deciding factor.
can be done to fix a design bug (exceptions apply).
9 Preferred for prototyping and validating a design or concept. Many ASICs
ASIC designers need to care for everything from RTL down to reset tree,
are prototyped using FPGAs themselves! Major processor manufacturers
clock tree, physical layout and routing, process node, manufacturing
themselves use FPGAs to validate their System-on-Chips (SoCs). It is easier
constraints (DFM), testing constraints (DFT) etc. Generally, each of the
to make sure design is working correctly as intended using FPGA
mentioned area is handled by different specialist person.
prototyping.
10 FPGA designers generally do not need to care for back-end design.
Everything is handled by synthesis and routing tools which make sure the 3-87
design works as described in the RTL code and meets timing. So, designers
can focus into getting the RTL design done.