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1.1.2 CMOS Fabrication

The document outlines the 14 step process for fabricating a CMOS device using an n-well process. It starts with an oxidized p-type substrate and involves steps like photolithography, etching, doping and metallization to form n-wells, transistors, and contacts. It also compares the n-well process to p-well and notes advantages like lower substrate bias effects and parasitic capacitances for n-well.

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18 views19 pages

1.1.2 CMOS Fabrication

The document outlines the 14 step process for fabricating a CMOS device using an n-well process. It starts with an oxidized p-type substrate and involves steps like photolithography, etching, doping and metallization to form n-wells, transistors, and contacts. It also compares the n-well process to p-well and notes advantages like lower substrate bias effects and parasitic capacitances for n-well.

Uploaded by

lokeshsai423
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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CMOS FABRICATION

n – WELL PROCESS
Step 1: Si Substrate

Start with p- type substrate

p substrate
Step 2: Oxidation

Exposing to high-purity oxygen and hydrogen at approx.


1000oC in oxidation furnace

SiO2

p substrate
Step 3: Photoresist Coating

Photoresist is a light-sensitive organic polymer


Softens when exposed to light

Photoresist
SiO2

p substrate
Step 4: Masking

Expose photoresist through n-well mask

Uv rays

n-well mask

Photoresist
SiO2

p substrate
Step 5: Removal of Photoresist

Photoresist are removed by treating the wafer with


acidic or basic solution.

Photoresist
SiO2

p substrate
Step 6: Acid Etching

SiO2 is selectively removed from areas of wafer that are not


covered by photoresist by using hydrofluoric acid.

Photoresist
SiO2

p substrate
Step 7: Removal of Photoresist

Strip off the remaining photoresist

SiO2

p substrate
Step 8: Formation of n-well

n-well is formed with diffusion or ion implantation

SiO2

n well
Step 9: Removal of SiO2

Strip off the remaining oxide using HF

n well
p substrate

wafer with n-well


Step 10: Polysilicon deposition

Deposit very thin layer of gate oxide using Chemical


Vapor Deposition (CVD) process

Polysilicon
Thin gate oxide

n well
p substrate

Polysilicon
Thin gate oxide

n well
p substrate
Step 11: N- diffusion

N-diffusion forms nMOS source, drain, and n-well contact

n well
p substrate

Oxidation

n well
p substrate

Masking
Step 11: N- diffusion

Dopants were diffused or ion implantated

n+ n+ n+

n well
p substrate

Diffusion

Strip off oxide

n+ n+ n+
n well
p substrate
Step 12: P- diffusion

Similar set of steps form p+ diffusion regions for


pMOS source and drain and substrate contact

p+ n+ n+ p+ p+ n+
n well
p substrate
Step 13: Contact cuts
The devices are to be wired together
Cover chip with thick field oxide
Etch oxide where contact cuts are needed

Thick field oxide


p+ n+ n+ p+ p+ n+
n well
p substrate
Step 14: Metallization

Sputter on aluminum over whole wafer


Pattern to remove excess metal, leaving wires

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate
p-well CMOS process

The fabrication of p-well cmos process is


similar to n-well process except that p-wells acts as
substrate for the n-devices within the parent n-
substrate
Advantages of n-well process

n-well CMOS are superior to p-well because of


lower substrate bias effects on transistor threshold
voltage
lower parasitic capacitances associated with source
and drain region
Latch-up problems can be considerably reduced by
using a low resistivity epitaxial p-type substrate
However n-well process degrades the performance
of poorly performing p-type transistor
Twin -Tub Process Refer text book for more details
on fabrication of NMOS, PMOS and CMOS

NOTE: Refer text book for more details on fabrication of NMOS, PMOS and CMOS
Text book: Basic VLSI design : Pucknell, Douglas A

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