Chap 7
Chap 7
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing
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Chapter 7 – Specialized Routing
© KLMH
7.1 Introduction to Area Routing
7.2 Net Ordering in Area Routing
7.3 Non-Manhattan Routing
7.3.1 Octilinear Steiner Trees
7.3.2 Octilinear Maze Search
7.4 Basic Concepts in Clock Networks
7.4.1 Terminology
7.4.2 Problem Formulations for Clock-Tree Routing
7.5 Modern Clock Tree Synthesis
7.5.1 Constructing Trees with Zero Global Skew
7.5.2 Clock Tree Buffering in the Presence of Variation
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 2
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7 Specialized Routing
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System Specification
Partitioning
Architectural Design
ENTITY test is
port a: in bit;
end ENTITY test;
Functional Design Chip Planning
and Logic Design
Physical Design
Clock Tree Synthesis
Physical Verification
DRC and Signoff
LVS Signal Routing
ERC
Fabrication
Timing Closure
Chip
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 3
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7 Specialized Routing
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Routing
Multi-Stage Routing
of Signal Nets
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 4
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7 Specialized Routing
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· Area routing directly constructs metal routes for signal connections
(no global and detailed routing, Secs. 7.1-7.2)
· Non-Manhattan routing is presented in Sec. 7.3
· Clock signals and other nets that require special treatment
are discussed in Secs. 7.4-7.5
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 5
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7.1 Introduction to Area Routing
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· The goal of area routing is to route all nets in the design
- without global routing
- within the given layout space
- while meeting all geometric and electrical design rules
· Subject to
- technology constraints (number of routing layers, minimal wire width, etc.)
- electrical constraints (signal integrity, coupling, etc.)
- geometry constraints (preferred routing directions, wire pitch, etc.)
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 6
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7.1 Introduction to Area Routing
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Minimal wirelength: Alternative routing path:
4 4
IC3 IC3
1 1 1 1
1 1
IC1 IC2 IC1 IC2
4 4 4 4
Metal1
Metal2
Via
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 7
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7.1 Introduction to Area Routing
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Distance metric between two points P1 (x1,y1) and P2 (x2,y2)
Manhattan distance d M ( P1 , P2 ) x2 x1 y2 y1 Δx Δy
P1 dM
dE
dM P2
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 8
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7.1 Introduction to Area Routing
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· Multiple Manhattan shortest paths between two points
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 9
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7.1 Introduction to Area Routing
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· Multiple Manhattan shortest paths between two points
m = 210
y
x
Δx Δy Δx Δy (Δx Δy )!
m
Δx Δy Δx!Δy!
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 10
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7.1 Introduction to Area Routing
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· Two pairs of points may admit non-intersecting Manhattan shortest paths,
while their Euclidean shortest paths intersect (but not vice versa).
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 11
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7.1 Introduction to Area Routing
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· If all pairs of Manhattan shortest paths between two pairs of points intersect,
then so do Euclidean shortest paths.
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 12
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7.1 Introduction to Area Routing
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· The Manhattan distance dM is (slightly) larger than the Euclidean distance dE:
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 13
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7.2 Net Ordering in Area Routing
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7.1 Introduction to Area Routing
7.2 Net Ordering in Area Routing
7.3 Non-Manhattan Routing
7.3.1 Octilinear Steiner Trees
7.3.2 Octilinear Maze Search
7.4 Basic Concepts in Clock Networks
7.4.1 Terminology
7.4.2 Problem Formulations for Clock-Tree Routing
7.5 Modern Clock Tree Synthesis
7.5.1 Constructing Trees with Zero Global Skew
7.5.2 Clock Tree Buffering in the Presence of Variation
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 14
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7.2 Net Ordering in Area Routing
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Effect of net ordering on routability
A A A
B B B
A´ B´ A´ B´ A´ B´
Optimal routing of net A Optimal routing of net B Nets A and B can be routed
only with detours
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7.2 Net Ordering in Area Routing
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Effect of net ordering on total wirelength
A A
B B
B´ B´
A´ A´
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7.2 Net Ordering in Area Routing
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· For n nets, there are n! possible net orderings
Þ Constructive heuristics are used
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 17
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7.2 Net Ordering in Area Routing
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· Rule 1: For two nets i and j, if aspect ratio (i ) > aspect ratio (j ),
then i is routed before j
A A
B´ B´
A´ B A´ B
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 18
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7.2 Net Ordering in Area Routing
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· Rule 2: For two nets i and j, if the pins of i are contained within MBB(j ),
then i is routed before j
A′ C
A′
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 19
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7.2 Net Ordering in Area Routing
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· Rule 3: Let (net) be the number of pins within MBB(net) for net net.
For two nets i and j, if (i ) < (j ), then i is routed before j.
- For each net, consider the pins of other nets within its bounding box
- The net with the smallest number of such pins is routed first
- Ties are broken based on the number of pins that are contained
within the bounding box and on its edge
A B A B
C Pins C
D D´ Inside (Edge) π D D´
(net)
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 20
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7.3 Non-Manhattan Routing
© KLMH
7.1 Introduction to Area Routing
7.2 Net Ordering in Area Routing
7.3 Non-Manhattan Routing
7.3.1 Octilinear Steiner Trees
7.3.2 Octilinear Maze Search
7.4 Basic Concepts in Clock Networks
7.4.1 Terminology
7.4.2 Problem Formulations for Clock-Tree Routing
7.5 Modern Clock Tree Synthesis
7.5.1 Constructing Trees with Zero Global Skew
7.5.2 Clock Tree Buffering in the Presence of Variation
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 21
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7.3 Non-Manhattan Routing
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· Allow 45- or 60-degree segments in addition to horizontal and vertical segments
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 22
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7.3.1 Octilinear Steiner Trees
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· Route planning using octilinear Steiner minimum trees (OSMT)
· Generalize rectilinear Steiner trees by allowing segments
that extend in eight directions
· More freedom when placing Steiner points
1
3
2
5
4
6 7
8 9
10
11 12
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 23
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7.3.1 Octilinear Steiner Trees
© KLMH
Octilinear Steiner Tree Algorithm
T.-Y.; Chang, et. al.: Multilevel Full-Chip Routing for the X-Based Architecture
Output: heuristic octilinear minimum Steiner tree OST
OST = Ø
T = set of all three-pin nets of P found by Delaunay triangulation
sortedT = SORT(T,minimum octilinear distance)
for (i = 1 to |sortedT |)
subT = ROUTE(sortedT [i ] ) // route minimum tree over subT
ADD(OST,subT ) // add route to existing tree
IMPROVE(OST,subT ) // locally improve OST based on
subT
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 24
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7.3.1 Octilinear Steiner Trees
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(1) Triangulate
1 1
3 3
2 2
5 5
4 4
6 7 6 7
8 9 8 9
10 10
11 12 11 12
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7.3.1 Octilinear Steiner Trees
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(1) Triangulate (2) Add route to existing tree
1 1 1
3 3 3
2 2 2
5 5 5
4 4 4
6 7 6 7 6 7
8 9 8 9 8 9
10 10 10
11 12 11 12 11 12
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7.3.1 Octilinear Steiner Trees
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(1) Triangulate (2) Add route to existing tree (3) Locally improve OST
1 1 1
3 3 3
2 2 2
5 5 5
4 4 4
6 7 6 7 6 7
8 9 8 9 8 9
10 10 10
11 12 11 12 11 12
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 27
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7.3.1 Octilinear Steiner Trees
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Final OST after merging all subtrees (3) Locally improve OST
1 1
3 3
2 2
5 5
4 4
6 7 6 7
8 9 8 9
10 10
12 11 12
11
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7.3.2 Octilinear Maze Search
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3 3 3 3 3 3
2 2 2 2 2 3 2 2 2 2 2
1 1 1 2 1 1 1 2 3 2 1 1 1 2
1 S 1 2 1 S 1 2 3 2 1 S 1 2
1 1 1 2 1 1 1 2 3 2 1 1 1 2
2 2 2 2 2 3 2 2 2 2 2
T T 3 T 3 3 3 3
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7.3.2 Octilinear Maze Search
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S
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 30
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7.4 Basic Concepts in Clock Networks
© KLMH
7.1 Introduction to Area Routing
7.2 Net Ordering in Area Routing
7.3 Non-Manhattan Routing
7.3.1 Octilinear Steiner Trees
7.3.2 Octilinear Maze Search
7.4 Basic Concepts in Clock Networks
7.4.1 Terminology
7.4.2 Problem Formulations for Clock-Tree Routing
7.5 Modern Clock Tree Synthesis
7.5.1 Constructing Trees with Zero Global Skew
7.5.2 Clock Tree Buffering in the Presence of Variation
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 31
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7.4.1 Terminology
© KLMH
· A clock routing instance (clock net) is represented by n+1 terminals,
where s0 is designated as the source, and S = {s1,s2, … ,sn} is designated
as sinks
- Let si, 0 ≤ i ≤ n, denote both a terminal and its location
· The clock-tree topology (clock tree) is a rooted binary tree G with n leaves
corresponding to the set of sinks
- Internal nodes = Steiner points
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 32
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7.4.1 Terminology
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Clock routing Connection topology Embedding
problem instance
s1 s0 s1
s2 u1 s2
s0 u2 s0
s3 s5 s3 s5
u1 u3 u4
u3 u2 u4
s4 s6 s4 s6
s1 s2 s3 s4 s5 s6
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7.4.1 Terminology
© KLMH
· Clock skew: (maximum) difference in clock signal arrival times between sinks
skew(T ) max | t ( s0 , si ) t ( s0 , s j ) |
s i , s j S
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 34
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7.4.2 Problem Formulations for Clock-Tree Routing
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· Zero skew: zero-skew tree (ZST)
- ZST problem
· Useful skew: correct chip timing only requires control of the local skews
between pairs of interconnected flip-flops or latches
- Useful skew formulation is based on analysis of local skew constraints
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 35
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7.5 Modern Clock Tree Synthesis
© KLMH
7.1 Introduction to Area Routing
7.2 Net Ordering in Area Routing
7.3 Non-Manhattan Routing
7.3.1 Octilinear Steiner Trees
7.3.2 Octilinear Maze Search
7.4 Basic Concepts in Clock Networks
7.4.1 Terminology
7.4.2 Problem Formulations for Clock-Tree Routing
7.5 Modern Clock Tree Synthesis
7.5.1 Constructing Trees with Zero Global Skew
7.5.2 Clock Tree Buffering in the Presence of Variation
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 36
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7.5 Modern Clock Tree Synthesis
© KLMH
· A clock tree should have low skew, while delivering the same signal
to every sequential gate
(1) Initial tree construction (Sec. 7.5.1) with one of these scenarios
- Construct a regular clock tree, largely independent of sink locations
- Simultaneously determine a topology and an embedding
- Construct only the embedding, given a clock-tree topology as input
(2) Clock buffer insertion and several subsequent skew optimizations (Sec. 7.5.2)
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 37
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7.5.1 Constructing Trees with Zero Global Skew
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H-tree
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 38
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7.5.1 Constructing Trees with Zero Global Skew
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Method of Means and Medians (MMM)
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 39
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7.5.1 Constructing Trees with Zero Global Skew
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Method of Means and Medians (MMM)
Find the Partition S by Find the center Connect the Final result after
center of the median of gravity for the center of gravity recursively
gravity left and right of S with the performing MMM
subsets of S centers of on each subset
gravity of the
left and right
subsets
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 40
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7.5.1 Constructing Trees with Zero Global Skew
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Method of Means and Medians (MMM)
if (|S| ≤ 1)
return
(x0,y0) = (xc(S),yc(S)) // center of mass for S
(SA,SB) = PARTITION(S) // median to determine SA and SB
(xA,yA) = (xc(SA),yc(SA)) // center of mass for SA
(xB,yB) = (xc(SB),yc(SB)) // center of mass for SB
ROUTE(T,x0,y0,xA,yA) // connect center of mass of S to
ROUTE(T,x0,y0,xB,yB) // center of mass of SA and SB
BASIC_MMM(SA,T) // recursively route SA
BASIC_MMM(SB,T) // recursively route SB
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 41
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7.5.1 Constructing Trees with Zero Global Skew
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Recursive Geometric Matching (RGM)
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 42
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7.5.1 Constructing Trees with Zero Global Skew
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Recursive Geometric Matching (RGM)
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 43
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7.5.1 Constructing Trees with Zero Global Skew
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Recursive Geometric Matching (RGM)
Input: set of sinks S, empty tree T
Output: clock tree T
if (|S| ≤ 1)
return
M = min-cost geometric matching over S
S’ = Ø
foreach (<Pi,Pj > M)
TPi = subtree of T rooted at Pi
TPj = subtree of T rooted at Pj
tp = tapping point on (Pi,Pj) // point that minimizes the skew of
// the tree Ttp = TPi U TPj U
(Pi,Pj)
ADD(S’,tp) // add tp to S’
ADD(T,(Pi,Pj)) // add matching segment (Pi,Pj) to T
if (|S| % 2 == 1) // if |S| is odd, add unmatched node
VLSI ADD(S’, unmatched
Physical Design: node)
From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 44
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7.5.1 Constructing Trees with Zero Global Skew
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Exact Zero Skew
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 45
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7.5.1 Constructing Trees with Zero Global Skew
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Exact Zero Skew
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7.5.1 Constructing Trees with Zero Global Skew
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Deferred-Merge Embedding (DME)
· Defers the choice of merging (tapping) points for subtrees of the clock tree
· Needs a tree topology as input
· Weakness in earlier algorithms:
- Determine locations of internal nodes of the clock tree too early;
once a centroid is found, it is never changed
· Basic idea:
- Two sinks in general position will have an infinite number of midpoints,
creating a tilted line segment – Manhattan arc
- Manhattan arc: same minimum wirelength and exact zero skew
- Selection of embedding points for internal nodes on Manhattan arc
will be delayed for as long as possible
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 47
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7.5.1 Constructing Trees with Zero Global Skew
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Deferred-Merge Embedding (DME)
s1 s2
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7.5.1 Constructing Trees with Zero Global Skew
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Deferred-Merge Embedding (DME)
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 49
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7.5.1 Constructing Trees with Zero Global Skew
© KLMH
Deferred-Merge Embedding (DME) Tilted Rectangular Region (TRR)
for the Manhattan arc of s1 and s2
with a radius of two units
s1 s1
Core
Radius
s2 s2
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7.5.1 Constructing Trees with Zero Global Skew
© KLMH
Deferred-Merge Embedding (DME) Merging segment for node u3
(the parent of nodes u1 and u2) is the
locus of feasible locations of u3 with
zero skew and minimum wirelength
ms(u1) ms(u2)
u3
s1 s3 trr(u2)
u1 u2
s4
trr(u1) |eu2 |
s1 |eu1 | s2
s2 s3 s4
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 51
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7.5.1 Constructing Trees with Zero Global Skew
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Deferred-Merge Embedding (DME)
s2 s7
s6 s1 s1 s8
s8
s3 s5 s7 s2 s7
s4 s0
s2
s6 s6
s1 s5
s8 s3 s3 s5
s4 s0
s2 s0 s4
s7
s3 s5
s4 s0
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 52
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7.5.1 Constructing Trees with Zero Global Skew
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Deferred-Merge Embedding (DME)
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7.5.1 Constructing Trees with Zero Global Skew
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Deferred-Merge Embedding (DME)
|epar|
trr(par) pl(par)
ms(v)
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7.5.1 Constructing Trees with Zero Global Skew
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Deferred-Merge Embedding (DME)
s3 s5
s4 s0
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 55
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7.5.1 Constructing Trees with Zero Global Skew
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Deferred-Merge Embedding (DME)
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 56
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7.5.2 Clock Tree Buffering in the Presence of Variation
© KLMH
· To address challenging skew constraints, a clock tree
undergoes several optimization steps, including
- Geometric clock tree construction
- Initial clock buffer insertion
- Clock buffer sizing
- Wire sizing
- Wire snaking
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 57
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Summary of Chapter 7 – Area Routing
© KLMH
· Area routing: avoiding the division into global and detailed routing
- Doing everything at once, subject to design rules
- Small netlists with complicated constraints
- Analog, MCM and PCB routing
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 58
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Summary of Chapter 7 – Non-Manhattan Tree Routing
© KLMH
· Recall that Manhattan routing is dictated by the limitations
of modern semiconductor manufacturing for thin wires
· Non-Manhattan connections
- Diagonal (45- or 60-degree) segments in addition to horizontal and vertical segments
- Create more freedom to place Steiner points
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 59
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Summary of Chapter 7 – Clock Network Routing
© KLMH
· Similar to signal-net routing, except for
- Very large numbers of sinks
- The need to equalize propagation delays from the root to sinks
- Longer routes (to satisfy the equalization constraint)
- Typical algorithms determine topology first, then geometric embedding
· Clock skew
- Consider propagation delay from the root to each sink
- Skew is the maximal pairwise difference between delays (over all pairs of sinks)
- May be limited to sinks that are within distance d > 0 (local skew)
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 60
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Summary of Chapter 7 – Modern Clock Tree Synthesis
© KLMH
· Initial clock tree construction
- Topology determination (MMM or RGM)
- DME embedding (different flavors for ZST and BST)
- Working with the Elmore delay model requires more effort
than working with linear delay models
· Geometric obstacles (e.g., macros)
- May require detours
- Can be handled during DME (complicated) or during post-processing
(often achieves as good results)
· Clock-tree optimization
- Buffer insertion
- Buffer sizing
- Wire sizing
- Wire snaking by small amounts
- Decreasing the impact of process variability
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 61
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