© KLMH

Chapter 7 – Specialized Routing

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing

Lienig
 Chapter 7 – Specialized Routing

© KLMH
7.1 Introduction to Area Routing
7.2 Net Ordering in Area Routing
7.3 Non-Manhattan Routing
7.3.1 Octilinear Steiner Trees
7.3.2 Octilinear Maze Search
7.4 Basic Concepts in Clock Networks
7.4.1 Terminology
7.4.2 Problem Formulations for Clock-Tree Routing
7.5 Modern Clock Tree Synthesis
7.5.1 Constructing Trees with Zero Global Skew
7.5.2 Clock Tree Buffering in the Presence of Variation

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 2

Lienig
 7 Specialized Routing

© KLMH
System Specification

Partitioning
Architectural Design
ENTITY test is
port a: in bit;
end ENTITY test;
Functional Design Chip Planning
and Logic Design

Circuit Design Placement

Physical Design
Clock Tree Synthesis

Physical Verification
DRC and Signoff
LVS Signal Routing
ERC
Fabrication

Timing Closure

© 2022 Springer Verlag

Packaging and Testing

Chip

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 3

Lienig
 7 Specialized Routing

© KLMH
Routing

Multi-Stage Routing
of Signal Nets

Global Detailed Timing-Driven Large Single- Geometric

Routing Routing Routing Net Routing Techniques
Coarse-grain Fine-grain Net topology Power (VDD) Non-Manhattan
assignment of assignment optimization and Ground and
routes to of routes to and resource (GND) clock routing
routing regions routing tracks allocation to routing (Chap. 7)
(Chap. 5) (Chap. 6) critical nets (Chap. 3)
(Chap. 8)

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 4

Lienig
 7 Specialized Routing

© KLMH
· Area routing directly constructs metal routes for signal connections
(no global and detailed routing, Secs. 7.1-7.2)
· Non-Manhattan routing is presented in Sec. 7.3
· Clock signals and other nets that require special treatment
are discussed in Secs. 7.4-7.5

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 5

Lienig
 7.1 Introduction to Area Routing

© KLMH
· The goal of area routing is to route all nets in the design
- without global routing
- within the given layout space
- while meeting all geometric and electrical design rules

· Area routing performs the following optimizations

- minimizing the total routed length and number of vias of all nets
- minimizing the total area of wiring and the number of routing layers
- minimizing the circuit delay and ensuring an even wire density
- avoiding harmful capacitive coupling between neighboring routes

· Subject to
- technology constraints (number of routing layers, minimal wire width, etc.)
- electrical constraints (signal integrity, coupling, etc.)
- geometry constraints (preferred routing directions, wire pitch, etc.)

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 6

Lienig
 7.1 Introduction to Area Routing

© KLMH
Minimal wirelength: Alternative routing path:

4 4
IC3 IC3
1 1 1 1
1 1
IC1 IC2 IC1 IC2
4 4 4 4

Metal1
Metal2
Via

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 7

Lienig
 7.1 Introduction to Area Routing

© KLMH
Distance metric between two points P1 (x1,y1) and P2 (x2,y2)

Euclidean distance d E ( P1 , P2 )  ( x2  x1 ) 2  ( y 2  y1 ) 2  (Δx) 2  (Δy ) 2

Manhattan distance d M ( P1 , P2 )  x2  x1  y2  y1  Δx  Δy

P1 dM

dE

dM P2

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 8

Lienig
 7.1 Introduction to Area Routing

© KLMH
· Multiple Manhattan shortest paths between two points

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 9

Lienig
 7.1 Introduction to Area Routing

© KLMH
· Multiple Manhattan shortest paths between two points

m = 210

y

x

With no obstacles, the number of Manhattan shortest paths in an Δx × Δy region is

 Δx  Δy   Δx  Δy  (Δx  Δy )!
m       
 Δx   Δy  Δx!Δy!
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 10

Lienig
 7.1 Introduction to Area Routing

© KLMH
· Two pairs of points may admit non-intersecting Manhattan shortest paths,
while their Euclidean shortest paths intersect (but not vice versa).

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 11

Lienig
 7.1 Introduction to Area Routing

© KLMH
· If all pairs of Manhattan shortest paths between two pairs of points intersect,
then so do Euclidean shortest paths.

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 12

Lienig
 7.1 Introduction to Area Routing

© KLMH
· The Manhattan distance dM is (slightly) larger than the Euclidean distance dE:

1.41 worst case: a square where Δx  Δy

dM
 1.27 on average, without obstacles
dE
1.15 on average, with obstacles

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 13

Lienig
 7.2 Net Ordering in Area Routing

© KLMH
7.1 Introduction to Area Routing
7.2 Net Ordering in Area Routing
7.3 Non-Manhattan Routing
7.3.1 Octilinear Steiner Trees
7.3.2 Octilinear Maze Search
7.4 Basic Concepts in Clock Networks
7.4.1 Terminology
7.4.2 Problem Formulations for Clock-Tree Routing
7.5 Modern Clock Tree Synthesis
7.5.1 Constructing Trees with Zero Global Skew
7.5.2 Clock Tree Buffering in the Presence of Variation

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 14

Lienig
 7.2 Net Ordering in Area Routing

© KLMH
Effect of net ordering on routability

A A A
B B B

A´ B´ A´ B´ A´ B´

Optimal routing of net A Optimal routing of net B Nets A and B can be routed
only with detours

© 2022 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 15

Lienig
 7.2 Net Ordering in Area Routing

© KLMH
Effect of net ordering on total wirelength

A A
B B
B´ B´

A´ A´

Routing net A first Routing net B first

© 2022 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 16

Lienig
 7.2 Net Ordering in Area Routing

© KLMH
· For n nets, there are n! possible net orderings
Þ Constructive heuristics are used

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 17

Lienig
 7.2 Net Ordering in Area Routing

© KLMH
· Rule 1: For two nets i and j, if aspect ratio (i ) > aspect ratio (j ),
then i is routed before j

A A
B´ B´
A´ B A´ B

© 2022 Springer Verlag

Net A has a higher aspect ratio Routing net B first results
of its bounding box; routing A in longer total wirelength
first results in shorter total wirlength

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 18

Lienig
 7.2 Net Ordering in Area Routing

© KLMH
· Rule 2: For two nets i and j, if the pins of i are contained within MBB(j ),
then i is routed before j

Constraint Graph Net Ordering

C C
A A A
B B
D Ordering D-A-C-B D D′
D′
B D or D-C-B-A
(not D-B-A-C)
C´ B′ C´ B′

A′ C
A′

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 19

Lienig
 7.2 Net Ordering in Area Routing

© KLMH
· Rule 3: Let (net) be the number of pins within MBB(net) for net net.
For two nets i and j, if (i ) < (j ), then i is routed before j.
- For each net, consider the pins of other nets within its bounding box
- The net with the smallest number of such pins is routed first
- Ties are broken based on the number of pins that are contained
within the bounding box and on its edge

A B A B
C Pins C
D D´ Inside (Edge) π D D´
(net)

A´ E MBB (A) D (B,C,D) 3

A´ E
B - (A,C,D) 3
C - (A) 1
C´ D - (-) 0 C´
E´ E - (A,C) 2
E´
B´ B´

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 20

Lienig
 7.3 Non-Manhattan Routing

© KLMH
7.1 Introduction to Area Routing
7.2 Net Ordering in Area Routing
7.3 Non-Manhattan Routing
7.3.1 Octilinear Steiner Trees
7.3.2 Octilinear Maze Search
7.4 Basic Concepts in Clock Networks
7.4.1 Terminology
7.4.2 Problem Formulations for Clock-Tree Routing
7.5 Modern Clock Tree Synthesis
7.5.1 Constructing Trees with Zero Global Skew
7.5.2 Clock Tree Buffering in the Presence of Variation

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 21

Lienig
 7.3 Non-Manhattan Routing

© KLMH
· Allow 45- or 60-degree segments in addition to horizontal and vertical segments

· λ-geometry, where λ represents the number of possible routing directions

and the angles  / λ at which they can be oriented
- λ = 2 (90 degrees): Manhattan routing (four routing directions)
- λ = 3 (60 degrees): Y-routing (six routing directions)
- λ = 4 (45 degrees): X-routing (eight routing directions)

· Non-Manhattan routing is primarily employed

on printed circuit boards (PCBs)

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 22

Lienig
 7.3.1 Octilinear Steiner Trees

© KLMH
· Route planning using octilinear Steiner minimum trees (OSMT)
· Generalize rectilinear Steiner trees by allowing segments
that extend in eight directions
· More freedom when placing Steiner points

1
3
2
5
4
6 7

8 9

10
11 12

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 23

Lienig
 7.3.1 Octilinear Steiner Trees

© KLMH
Octilinear Steiner Tree Algorithm

Input: set of all pins P and their coordinates

T.-Y.; Chang, et. al.: Multilevel Full-Chip Routing for the X-Based Architecture
Output: heuristic octilinear minimum Steiner tree OST

OST = Ø
T = set of all three-pin nets of P found by Delaunay triangulation
sortedT = SORT(T,minimum octilinear distance)
for (i = 1 to |sortedT |)
subT = ROUTE(sortedT [i ] ) // route minimum tree over subT
ADD(OST,subT ) // add route to existing tree
IMPROVE(OST,subT ) // locally improve OST based on
subT

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 24

Lienig
 7.3.1 Octilinear Steiner Trees

© KLMH
(1) Triangulate
1 1
3 3
2 2
5 5
4 4
6 7 6 7

8 9 8 9

10 10
11 12 11 12

© 2022 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 25

Lienig
 7.3.1 Octilinear Steiner Trees

© KLMH
(1) Triangulate (2) Add route to existing tree
1 1 1
3 3 3
2 2 2
5 5 5
4 4 4
6 7 6 7 6 7

8 9 8 9 8 9

10 10 10
11 12 11 12 11 12

© 2022 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 26

Lienig
 7.3.1 Octilinear Steiner Trees

© KLMH
(1) Triangulate (2) Add route to existing tree (3) Locally improve OST
1 1 1
3 3 3
2 2 2
5 5 5
4 4 4
6 7 6 7 6 7

8 9 8 9 8 9

10 10 10
11 12 11 12 11 12

© 2022 Springer Verlag

cost = 6 cost ≈ 5.7

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 27

Lienig
 7.3.1 Octilinear Steiner Trees

© KLMH
Final OST after merging all subtrees (3) Locally improve OST
1 1
3 3
2 2
5 5
4 4
6 7 6 7

8 9 8 9

10 10
12 11 12
11

© 2022 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 28

Lienig
 7.3.2 Octilinear Maze Search

© KLMH
3 3 3 3 3 3
2 2 2 2 2 3 2 2 2 2 2
1 1 1 2 1 1 1 2 3 2 1 1 1 2
1 S 1 2 1 S 1 2 3 2 1 S 1 2
1 1 1 2 1 1 1 2 3 2 1 1 1 2
2 2 2 2 2 3 2 2 2 2 2
T T 3 T 3 3 3 3

Expansion (1) Expansion (2) Backtracing

© 2022 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 29

Lienig
 7.3.2 Octilinear Maze Search

© KLMH
S

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 30

Lienig
 7.4 Basic Concepts in Clock Networks

© KLMH
7.1 Introduction to Area Routing
7.2 Net Ordering in Area Routing
7.3 Non-Manhattan Routing
7.3.1 Octilinear Steiner Trees
7.3.2 Octilinear Maze Search
7.4 Basic Concepts in Clock Networks
7.4.1 Terminology
7.4.2 Problem Formulations for Clock-Tree Routing
7.5 Modern Clock Tree Synthesis
7.5.1 Constructing Trees with Zero Global Skew
7.5.2 Clock Tree Buffering in the Presence of Variation

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 31

Lienig
 7.4.1 Terminology

© KLMH
· A clock routing instance (clock net) is represented by n+1 terminals,
where s0 is designated as the source, and S = {s1,s2, … ,sn} is designated
as sinks
- Let si, 0 ≤ i ≤ n, denote both a terminal and its location

· A clock routing solution consists of a set of wire segments that connect

all terminals of the clock net, so that a signal generated at the source
propagates to all of the sinks
- Two aspects of clock routing solution: topology and geometric embedding

· The clock-tree topology (clock tree) is a rooted binary tree G with n leaves
corresponding to the set of sinks
- Internal nodes = Steiner points

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 32

Lienig
 7.4.1 Terminology

© KLMH
Clock routing Connection topology Embedding
problem instance

s1 s0 s1
s2 u1 s2
s0 u2 s0
s3 s5 s3 s5
u1 u3 u4
u3 u2 u4
s4 s6 s4 s6
s1 s2 s3 s4 s5 s6

© 2022 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 33

Lienig
 7.4.1 Terminology

© KLMH
· Clock skew: (maximum) difference in clock signal arrival times between sinks

skew(T )  max | t ( s0 , si )  t ( s0 , s j ) |
s i , s j S

· Local skew: maximum difference in arrival times of the clock signal

at the clock pins of two or more related sinks
- Sinks within distance d > 0
- Flip-flops or latches connected by a directed signal path

· Global skew: maximum difference in arrival times of the clock signal

at the clock pins of any two (related or unrelated) sinks
- Difference between shortest and longest source-sink path delays
in the clock distribution network
- The term “skew” typically refers to “global skew”

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 34

Lienig
 7.4.2 Problem Formulations for Clock-Tree Routing

© KLMH
· Zero skew: zero-skew tree (ZST)
- ZST problem

· Bounded skew: true ZST may not be necessary in practice

- Signoff timing analysis is sufficient with a non-zero skew bound
- In addition to final (signoff) timing, this relaxation can be useful with intermediate
delay models when it facilitates reductions in the length of the tree
- Bounded-Skew Tree (BST) problem

· Useful skew: correct chip timing only requires control of the local skews
between pairs of interconnected flip-flops or latches
- Useful skew formulation is based on analysis of local skew constraints

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 35

Lienig
 7.5 Modern Clock Tree Synthesis

© KLMH
7.1 Introduction to Area Routing
7.2 Net Ordering in Area Routing
7.3 Non-Manhattan Routing
7.3.1 Octilinear Steiner Trees
7.3.2 Octilinear Maze Search
7.4 Basic Concepts in Clock Networks
7.4.1 Terminology
7.4.2 Problem Formulations for Clock-Tree Routing
7.5 Modern Clock Tree Synthesis
7.5.1 Constructing Trees with Zero Global Skew
7.5.2 Clock Tree Buffering in the Presence of Variation

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 36

Lienig
 7.5 Modern Clock Tree Synthesis

© KLMH
· A clock tree should have low skew, while delivering the same signal
to every sequential gate

· Clock tree synthesis is performed in two steps:

(1) Initial tree construction (Sec. 7.5.1) with one of these scenarios
- Construct a regular clock tree, largely independent of sink locations
- Simultaneously determine a topology and an embedding
- Construct only the embedding, given a clock-tree topology as input

(2) Clock buffer insertion and several subsequent skew optimizations (Sec. 7.5.2)

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 37

Lienig
 7.5.1 Constructing Trees with Zero Global Skew

© KLMH
H-tree

· Exact zero skew due to the symmetry of the H-tree

· Used for top-level clock distribution, not for the entire clock tree
- Blockages can spoil the symmetry of an H-tree
- Non-uniform sink locations and varying sink capacitances
also complicate the design of H-trees

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 38

Lienig
 7.5.1 Constructing Trees with Zero Global Skew

© KLMH
Method of Means and Medians (MMM)

· Can deal with arbitrary locations of clock sinks

· Basic idea:
- Recursively partition the set of terminals into two subsets of equal size (median)
- Connect the center of gravity (COG) of the set to the centers of gravity
of the two subsets (the mean)

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 39

Lienig
 7.5.1 Constructing Trees with Zero Global Skew

© KLMH
Method of Means and Medians (MMM)

Find the Partition S by Find the center Connect the Final result after
center of the median of gravity for the center of gravity recursively
gravity left and right of S with the performing MMM
subsets of S centers of on each subset
gravity of the
left and right
subsets

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 40

Lienig
 7.5.1 Constructing Trees with Zero Global Skew

© KLMH
Method of Means and Medians (MMM)

Input: set of sinks S, empty tree T

Output: clock tree T

if (|S| ≤ 1)
return
(x0,y0) = (xc(S),yc(S)) // center of mass for S
(SA,SB) = PARTITION(S) // median to determine SA and SB
(xA,yA) = (xc(SA),yc(SA)) // center of mass for SA
(xB,yB) = (xc(SB),yc(SB)) // center of mass for SB
ROUTE(T,x0,y0,xA,yA) // connect center of mass of S to
ROUTE(T,x0,y0,xB,yB) // center of mass of SA and SB
BASIC_MMM(SA,T) // recursively route SA
BASIC_MMM(SB,T) // recursively route SB
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 41

Lienig
 7.5.1 Constructing Trees with Zero Global Skew

© KLMH
Recursive Geometric Matching (RGM)

· RGM proceeds in a bottom-up fashion

- Compare to MMM, which is a top-down algorithm
· Basic idea:
- Recursively determine a minimum-cost geometric matching of n sinks
- Find a set of n / 2 line segments that match n endpoints and minimize total length
(subject to the matching constraint)
- After each matching step, a balance or tapping point is found
on each matching segment to preserve zero skew to the associated sinks
- The set of n / 2 tapping points then forms the input to the next matching step

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 42

Lienig
 7.5.1 Constructing Trees with Zero Global Skew

© KLMH
Recursive Geometric Matching (RGM)

Set of n Min-cost Find balance or Min-cost Final result after

sinks S geometric tapping points geometric recursively
matching (point that achieves matching performing RGM
zero skew in the on each subset
subtree, not always

© 2022 Springer Verlag

midpoint)

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 43

Lienig
 7.5.1 Constructing Trees with Zero Global Skew

© KLMH
Recursive Geometric Matching (RGM)
Input: set of sinks S, empty tree T
Output: clock tree T

if (|S| ≤ 1)
return
M = min-cost geometric matching over S
S’ = Ø
foreach (<Pi,Pj >  M)
TPi = subtree of T rooted at Pi
TPj = subtree of T rooted at Pj
tp = tapping point on (Pi,Pj) // point that minimizes the skew of
// the tree Ttp = TPi U TPj U
(Pi,Pj)
ADD(S’,tp) // add tp to S’
ADD(T,(Pi,Pj)) // add matching segment (Pi,Pj) to T
if (|S| % 2 == 1) // if |S| is odd, add unmatched node
VLSI ADD(S’, unmatched
Physical Design: node)
From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 44

Lienig
 7.5.1 Constructing Trees with Zero Global Skew

© KLMH
Exact Zero Skew

· Adopts a bottom-up process of matching subtree roots and merging

the corresponding subtrees, similar to RGM
· Two important improvements:
- Finds exact zero-skew tapping points with respect to the Elmore delay model
rather than the linear delay model
- Maintains exact delay balance even when two subtrees with very different
source-sink delays are matched (by wire elongation)

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 45

Lienig
 7.5.1 Constructing Trees with Zero Global Skew

© KLMH
Exact Zero Skew

Tapping point tp R(w1)

t(Ts1
z C(w1) C(w1) C(s1))
2 2
z 1–z Tapping point tp,
w1 w2 where Elmore delay
s1 s2 R(w2)
to sinks is equalized t(Ts2
1–z C(w2) C(w2) C(s2))
2 2
Subtree Ts1 Subtree Ts2

© 2022 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 46

Lienig
 7.5.1 Constructing Trees with Zero Global Skew

© KLMH
Deferred-Merge Embedding (DME)

· Defers the choice of merging (tapping) points for subtrees of the clock tree
· Needs a tree topology as input
· Weakness in earlier algorithms:
- Determine locations of internal nodes of the clock tree too early;
once a centroid is found, it is never changed
· Basic idea:
- Two sinks in general position will have an infinite number of midpoints,
creating a tilted line segment – Manhattan arc
- Manhattan arc: same minimum wirelength and exact zero skew
- Selection of embedding points for internal nodes on Manhattan arc
will be delayed for as long as possible

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 47

Lienig
 7.5.1 Constructing Trees with Zero Global Skew

© KLMH
Deferred-Merge Embedding (DME)

Euclidean midpoint Euclidean midpoint

s2 s1
s1 s2

s1 s2

Locus of all Sinks are aligned, hence, Manhattan arc

Manhattan midpoints is has zero length
a Manhattan arc in the
Manhattan geometry

© 2022 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 48

Lienig
 7.5.1 Constructing Trees with Zero Global Skew

© KLMH
Deferred-Merge Embedding (DME)

· Embeds internal nodes of the given topology G via a two-phase process

· First phase is bottom-up

- Determines all possible locations of internal nodes of G
consistent with a minimum-cost ZST T
- Output: “tree of line segments”, with each line segment being
the locus of possible placements of an internal node of T

· Second phase is top-down

- Chooses the exact locations of all internal nodes in T
- Output: fully embedded, minimum-cost ZST with topology G

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 49

Lienig
 7.5.1 Constructing Trees with Zero Global Skew

© KLMH
Deferred-Merge Embedding (DME) Tilted Rectangular Region (TRR)
for the Manhattan arc of s1 and s2
with a radius of two units

s1 s1
Core
Radius
s2 s2

© 2022 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 50

Lienig
 7.5.1 Constructing Trees with Zero Global Skew

© KLMH
Deferred-Merge Embedding (DME) Merging segment for node u3
(the parent of nodes u1 and u2) is the
locus of feasible locations of u3 with
zero skew and minimum wirelength
ms(u1) ms(u2)

u3
s1 s3 trr(u2)
u1 u2
s4
trr(u1) |eu2 |
s1 |eu1 | s2
s2 s3 s4

© 2022 Springer Verlag

ms(u3)

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 51

Lienig
 7.5.1 Constructing Trees with Zero Global Skew

© KLMH
Deferred-Merge Embedding (DME)

Build Tree of Segments Algorithm (DME Bottom-Up Phase)

s1
s8

s2 s7
s6 s1 s1 s8
s8
s3 s5 s7 s2 s7
s4 s0
s2
s6 s6
s1 s5
s8 s3 s3 s5
s4 s0
s2 s0 s4
s7

© 2022 Springer Verlag

s6

s3 s5
s4 s0
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 52

Lienig
 7.5.1 Constructing Trees with Zero Global Skew

© KLMH
Deferred-Merge Embedding (DME)

Build Tree of Segments Algorithm (DME Bottom-Up Phase)

Input: set of sinks S and tree topology G(S,Top)

Output: merging segments ms(v) and edge lengths |ev|, v  G

foreach (node v  G, in bottom-up order)

if (v is a sink node) // if v is a terminal, then ms(v) is a
ms[v] = PL(v) // zero-length
Manhattan arc
else // otherwise, if v is an internal
node,
(a,b) = CHILDREN(v) // find v’s children and
CALC_EDGE_LENGTH(ea,eb) // calculate the edge
length
trr[a][core] = MS(a) // create trr(a) – find
merging segment
trr[a][radius] = |e |
VLSI Physical Design: From Graph Partitioning to Timing Closure a
// and radius of a
Chapter 7: Specialized Routing 53

Lienig
 7.5.1 Constructing Trees with Zero Global Skew

© KLMH
Deferred-Merge Embedding (DME)

Find Exact Locations (DME Top-Down Phase)

Possible locations of child node v

given the location of its parent node par

|epar|
trr(par) pl(par)
ms(v)

© 2022 Springer Verlag

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 54

Lienig
 7.5.1 Constructing Trees with Zero Global Skew

© KLMH
Deferred-Merge Embedding (DME)

Find Exact Locations (DME Top-Down Phase)

s1
s8
s7
s2
s6 s1 s1
s8 s8
s3 s5
s0 s7 s7
s4 s2 s2
s6 s6
s1 s8
s3 s5 s3 s5
s7 s4 s0 s0
s4
s2

© 2022 Springer Verlag

s6

s3 s5
s4 s0

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 55

Lienig
 7.5.1 Constructing Trees with Zero Global Skew

© KLMH
Deferred-Merge Embedding (DME)

Find Exact Locations (DME Top-Down Phase)

Input: set of sinks S, tree topology G, outputs of DME bottom-up phase

Output: minimum-cost zero-skew tree T with topology G

foreach (non-sink node v  G top-down order)

if (v is the root)
loc = any point in ms(v)
else
par = PARENT(v) // par is the parent of v
trr[par][core] = PL(par) // create trr(par) – find
merging segment
trr[par][radius] = |ev| // and radius of par
loc = any point in ms[v] ∩ trr[par]
pl[v] = loc

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 56

Lienig
 7.5.2 Clock Tree Buffering in the Presence of Variation

© KLMH
· To address challenging skew constraints, a clock tree
undergoes several optimization steps, including
- Geometric clock tree construction
- Initial clock buffer insertion
- Clock buffer sizing
- Wire sizing
- Wire snaking

· In the presence of process, voltage, and temperature variations,

such optimizations require modeling the impact of variations
- Variation model encapsulates the different parameters, such as width and thickness,
of each library element as well-defined random variables

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 57

Lienig
 Summary of Chapter 7 – Area Routing

© KLMH
· Area routing: avoiding the division into global and detailed routing
- Doing everything at once, subject to design rules
- Small netlists with complicated constraints
- Analog, MCM and PCB routing

· Manhattan vs Euclidean paths

- Euclidean paths are no longer than Manhattan, usually shorter
- Unique Euclidean shortest path
- Multiple Manhattan paths
- When Euclidean shortest paths intersect, there may exist Manhattan shortest paths
that do not (not vice versa)

· Net ordering is important in area routing

- Rule 1: nets with higher aspect ratio (less flexible) routed first
- Rule 2: nets surrounded by other nets (more constrained) routed first
- Rule 3: nets with more pins inside other net's bounding boxes routed first

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 58

Lienig
 Summary of Chapter 7 – Non-Manhattan Tree Routing

© KLMH
· Recall that Manhattan routing is dictated by the limitations
of modern semiconductor manufacturing for thin wires

· PCB routing is not subject to those limitations

- Can use shorter connections

· Non-Manhattan connections
- Diagonal (45- or 60-degree) segments in addition to horizontal and vertical segments
- Create more freedom to place Steiner points

· Octilinear Steiner Tree construction

- Algorithms are generally adapted from the Manhattan case
- Should produce results that are at least as good as the Manhattan case

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 59

Lienig
 Summary of Chapter 7 – Clock Network Routing

© KLMH
· Similar to signal-net routing, except for
- Very large numbers of sinks
- The need to equalize propagation delays from the root to sinks
- Longer routes (to satisfy the equalization constraint)
- Typical algorithms determine topology first, then geometric embedding

· Clock skew
- Consider propagation delay from the root to each sink
- Skew is the maximal pairwise difference between delays (over all pairs of sinks)
- May be limited to sinks that are within distance d > 0 (local skew)

· For a specified wire delay model

- ZST: Zero-Skew Tree routing requires that skew = 0
- BST: Bounded-Skew Tree routing requires that skew < Bound

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 60

Lienig
 Summary of Chapter 7 – Modern Clock Tree Synthesis

© KLMH
· Initial clock tree construction
- Topology determination (MMM or RGM)
- DME embedding (different flavors for ZST and BST)
- Working with the Elmore delay model requires more effort
than working with linear delay models
· Geometric obstacles (e.g., macros)
- May require detours
- Can be handled during DME (complicated) or during post-processing
(often achieves as good results)
· Clock-tree optimization
- Buffer insertion
- Buffer sizing
- Wire sizing
- Wire snaking by small amounts
- Decreasing the impact of process variability

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 7: Specialized Routing 61

Lienig