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17 views

Coa

Uploaded by

gagan.cse
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Bus

► A bus is a shared communication link (a single set of


wires used to connect multiple subsystems) that
needs to support a range of devices with widely
varying latencies and data transfer rates
► Buses are the electronic channels that allow the
various input / output and storage devices to
communicate with the CPU.
► Advantages
►Versatile – new devices can be added easily and
can be moved between computer systems that
use the same bus standard
►Low cost – a single set of wires is shared in
multiple ways
► Disadvantages
Creates a communication bottleneck – bus
bandwidth limits the maximum I/O
throughput

► The maximum bus speed is largely limited


by
 The length of the bus
 The number of devices on the bus
Performance Measures for I/O
There are two fundamental performance metrics for I/O
systems:
► Bandwidth: the amount of data that can be transferred in
unit time (units = bytes/time)
 This is a primary concern for applications which
transfer large amounts of data in big blocks.
 If you download large files, bandwidth will be the
limiting factor.
► Latency: the time taken for the smallest transfer (units =
time)
 This is a primary concern for programs that do many
small dependent transfers.
 It takes time for bits to travel across states, countries
and oceans!
System Bus
► Most modern computers use single bus
arrangement for connecting I/O devices to
CPU & Memory
► The bus enables all the devices connected to
it to exchange information
► Bus consists of 3 set of lines : Address,
Data, Control

4
Address Bus
► An address bus is a computer bus that is used
to specify a physical address.
► When a processor or DMA-enabled device
needs to read or write to a memory location, it
specifies that memory location on the address
bus
► The width of the address bus determines the
amount of memory a system can address. For
example, a system with a 32-bit address bus
can address 232 (4,294,967,296) memory
locations.
Control Bus
► The control bus carries commands from the
CPU and returns status signals from the
devices, for example if the data is being
read or written to the device the
appropriate line (read or write) will be active
► It determine the operation to be performed
Data Bus
► The data to be transferred will be placed on
Data bus
► The data lines of the bus carry information
between the source and the destination. This
information may consist of data, complex
commands, or Instructions.
► A data bus has many different defining
characteristics, but one of the most important
is its width. The width of a data bus refers to
the number of bits (electrical wires) that make
up the bus. Common data bus widths include
8, 16, 32, and 64-bit.
Hierarchical buses
► We could split the bus into different
segments.
► Since the CPU and memory need to
communicate so often, a shorter and faster
processor-memory bus can be dedicated to
them.
► A separate I/O bus would connect the
slower devices to each other, and eventually
to the processor.
Hierarchical buses
CPU Memory

Processor-memory bus

I/O bus

Hard disks CD-ROM Network Display


External buses
► External buses are provided to support the
frequent plugging and un-plugging of devices
 As a result their designs significantly differ
from internal buses
► Two modern external buses, Universal Serial
Bus (USB) and FireWire, have the following
(desirable) characteristics:
 Plug-and-play standards allow devices to be
configured with software, instead of flipping
switches or setting jumpers.
Hot plugging means that you don’t have to
turn off a machine to add or remove a
peripheral.
 The cable transmits power! No more power
cables or extension cords.
 Serial links are used, so the cable and
connectors are small.
Synchronous and Asynchronous
Communication
► If a Bus is Synchronous (e.g., processor-memory
buses)
 Includes a clock in the control lines and has a
fixed protocol for communication that is relative
to the clock
 Advantage: involves very little logic and can run
very fast
 Disadvantages:
►Every device communicating on the bus must
use same clock rate
►To avoid clock skew, they cannot be long if
they are fast
► Asynchronous bus (e.g., I/O buses)
 It is not clocked, so requires a handshaking
protocol and additional control lines
(ReadReq, Ack, DataRdy)
 Advantages:
►Can accommodate a wide range of devices
and device speeds
►Can be lengthened without worrying about
clock skew or synchronization problems
 Disadvantage: slower
Asynchronous Bus Handshaking
Protocol
 Output (read) data from memory to an I/O device

ReadReq 1
2
Data addr data
3
Ack 4 6
5 7
DataRdy

I/O device signals a request by raising ReadReq and putting the addr on
the data lines

1. Memory sees ReadReq, reads addr from data lines, and raises Ack
2. I/O device sees Ack and releases the ReadReq and data lines
3. Memory sees ReadReq go low and drops Ack
4. When memory has data ready, it places it on data lines and raises DataRdy
5. I/O device sees DataRdy, reads the data from data lines, and raises Ack
6. Memory sees Ack, releases the data lines, and drops DataRdy
7. I/O device sees DataRdy go low and drops Ack
Input Output
mechanism
Memory mapped I/O
► I/O devices and the memory share the
same address space, the arrangement is
called Memory-mapped I/O.
► In Memory-mapped I/O portions of address
space are assigned to I/O devices and reads
and writes to those addresses are
interpreted as commands to the I/O device.
► Memory-mapped I/O uses the same address
bus to address both memory and I/O devices - the
memory and registers of the I/O devices are
mapped to (associated with) address values. So
when an address is used by the CPU it may refer
to a portion of physical RAM, or it can instead refer
to memory of the I/O device

► theCPU instructions used to access the memory


are also used for accessing devices. Each I/O
device monitors the CPU's address bus and
responds to any of the CPU's access of address
space assigned to that device, connecting the data
bus to a desirable device's hardware register.
► Toaccommodate the I/O devices, areas of
the addresses used by the CPU must be
reserved for I/O and not be available for
normal physical memory.
Port-mapped I/O

► Port-mapped I/O uses a special class of CPU


instructions specifically for performing I/O.
► I/O devices have a separate address space from
general memory, either accomplished by an extra
"I/O" pin on the CPU's physical interface, or an
entire bus dedicated to I/O. Because the address
space for I/O is isolated from that for main
memory, this is sometimes referred to as isolated
I/O.

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