Chapter 1

Computer System Overview

Spring 2020 © 2020 by Greg Ozbirn, UTD, for 1

use with Stalling's 9th Ed. OS book
 Introduction
Computer system:
• Hardware
• Software
– Operating System (system software)
– Applications

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 Hardware
• Processor
– The processor (CPU) is the “brain” of the system.
– It fetches instructions from memory and executes them.
• Main memory
– Volatile storage for programs and data
• I/O modules
– Allow data to be moved to and from the computer and
I/O devices.
• System bus
– The pathway for data and instructions to move between
the processor, memory, and I/O modules.
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 Hardware Configuration

CPU

Input /
System I/O Modules
Output
Bus
Devices
Main
Memory

The system bus connects the CPU, I/O Modules, and Main Memory

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 Evolution of the Microprocessor
• The invention of the microprocessor enabled desktop and
handheld computing.
• A microprocessor is a processor contained on a single chip.
• Originally slower but now faster than multichip
processors.
• Modern microprocessors may have multiple processors on
a single chip, called processor ‘cores’.
• Each core might be able to support two logical processors
by sharing an execution unit.
• A modern microprocessor chip might contain 2 or 4 cores,
enabling a view of 4 to 8 logical processors.

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 Evolution of the Microprocessor
• GPU – Graphical Processing Unit.
– A GPU provides efficient computation on arrays of data using
SIMD (Single-Instruction Multiple Data) techniques.
– Originally for graphics, now used in general numeric processing,
including physics simulations, games, and large spreadsheets.

• DSP – Digital Signal Processor.

– A DSP can process a stream of data such as audio or video.

• Other supporting chips co-exist with the CPU to provide such things
as encoding/decoding video (codecs), or for encryption and security.

• SoC – System on a Chip.

– For handheld devices where many of the components (CPU, DSP,
GPU, Memory, etc.) are on a single chip. 7
 Instruction Cycle
• A program is a set of instructions to be executed in
memory.
• A simplified view of the processor consists of two phases,
fetch and execute.
• The fetch step retrieves an instruction from memory.
• The execute step carries out the instruction.
• After each fetch, the program counter (PC) is normally
incremented so that it is ready to fetch the next instruction.
• The fetched instruction loads into the IR.
• The instruction in the IR is then decoded to determine
what the processor should do.

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 Processing
Main Memory

Execute

CPU
Fetch Instruction

The CPU fetches an instruction from memory and executes it.

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 Instruction Execution

An “instruction cycle” is the processing of a single

instruction, involving the fetch cycle and execute cycle.
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 Instruction Actions
• Processor-memory
– transfer data between processor and memory
• Processor-I/O
– data transferred to or from a peripheral device
• Data processing
– arithmetic or logic operation on data
• Control
– alter sequence of execution (branch instruction)

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 Instruction and Data Formats
Example

Instruction:

0 3 4 15
Opcode Address

Data (integer):
0 1 15
Sign Magnitude

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 Instruction Format
• Notice that a machine will have a size for instructions like
16-bit or 32-bit based on its architecture.
• This limits the size of an instruction.
• If part of the instruction is an opcode and part an address,
then the portion set aside for the opcode determines how
many opcodes there can be, and the portion set aside for the
address determines how much memory is directly
addressable.
• For example, if 4 bit opcodes, then only 16 opcodes are
possible (which isn’t many).

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 Example Opcodes
• 0001 = Load AC from memory
• 0010 = Store AC to memory
• 0101 = Add to AC from memory

• AC is the “Accumulator” register. It is a register

commonly used for loading and storing values to memory
and doing arithmetic.

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 Interrupts
• Interrupts are a mechanism for interrupting the processor’s
execution in order to do something else.
• Common types of interrupts are:
– Program – instruction exceptions:
• arithmetic overflow
• division by zero
• execute illegal instruction
• reference outside user’s memory space
– Timer – system timer
– I/O – completion of I/O or I/O error.
– Hardware failure – power failure or memory parity
error. 16
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 Interrupts
• Interrupts improve processor utilization by notifying the
processor of an event versus making the processor wait.
• This frees the processor to do other processing.
• Without interrupts, the processor would have to keep
checking to see if an event has occurred.
• With interrupts, the processor is free to do something else
until the event occurs, at which time it will be notified.

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 Interrupts
• An example of using interrupts to improve processor
utilization is in processing I/O commands.
• Most I/O devices are much slower than the processor.
• Rather than have the processor wait for an I/O to finish,
the processor could continue processing and be interrupted
when an I/O finishes. This is much more efficient.
• The next slide illustrates this technique:

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Time 1 1
4 4
Processor
Wait I/O Operation
Interrupt 2a I/O Operation

5 5 Interrupt handler

2b
2
4
4 Interrupt 3a I/O Operation

Processor
Wait I/O Operation 5 Interrupt handler

5 3b

Without interrupts With interrupts

Program timing: Short I/O Wait 21

Interrupt Cycle

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 Interrupt Cycle
• After instruction execution, the processor checks to see if
an interrupt has occurred.
• If so, it executes an “Interrupt Handler”, which is code that
processes the interrupt.
• The processor must save system state (the registers) on the
stack before executing the interrupt handler, or the
interrupt handler may be written to preserve system state.
• The processor may have to determine which interrupt
handler to run for this interrupt.

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 Interrupt Processing
Memory

When an interrupt occurs, the CPU

Stack switches from executing the program
to executing the interrupt handler.

Interrupt
handler
CPU

Program System state is saved on the stack so

that execution can resume in the
program when the handler is finished as
if the interrupt had never occurred. 25
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 Multiple Interrupts
• It is possible for an interrupt to occur while another
interrupt is being processed.
• Two solutions:
– Disable interrupts while processing an interrupt.
Disadvantage: high-priority interrupt may wait too
long and lose data while waiting for a low-priority
interrupt to finish.
– Interrupt Priorities: lets high-priority interrupt execute
when processing low-priority interrupt. Interrupts low-
priority interrupt just like interrupting a program.

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 Memory Hierarchies
• Memory on a computer system is composed of a hierarchy
of differing kinds of memory.
• Generally these tradeoffs apply across the spectrum of
memory technologies:
– Faster access time, greater cost per bit
– Greater capacity, smaller cost per bit
– Greater capacity, slower access time.

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 Memory Hierarchies
• The computer system designer wants greater capacity for
larger programs and reduced cost per bit, but also wants
fast access times which requires lower capacity memories
having higher cost.
• Therefore, a single memory solution isn’t appropriate, that
is why a hierarchy of memory types is used.

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Decr. cost per bit
Incr. capacity
Incr. access time
Decr. freq. of access
by the processor.

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 Why does a Memory Hierarchy work?

• Locality of reference: program execution of instructions

and data occurs in clusters.
• Therefore, as long as a cluster is loaded high up in the
memory hierarchy, execution is fast until that cluster is
finished and the next cluster is loaded.
• If we think of program execution as a series of clusters
which can load into the highest memory level and execute,
then we can see that program execution can be quite fast.

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 Cache Memory
• Today most processors can execute instructions faster than
they can be retrieved from main memory.
• Cache memory sits between the processor and main
memory and exploits the principle of “locality of
reference” by keeping a “working set” of instructions and
data in its small but high-speed memory.

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 Cache Principles
• When the processor fetches an instruction, a block is read
into the cache.
• When the next instruction is fetched, there is a high
probability it is contained in the same cache block, which
can be accessed quickly.

• A cache consists of slots (or lines) of K words.

• Main memory is divided into blocks of K words.
• If main memory is size 2N words, then there are M=2N/K
blocks of memory.
• If C is the number of cache slots, C << M.
• Cache lines are addressed by a tag, which is some number
of high-order bits of the address.
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 Cache Example
• The hit ratio is the fraction of memory accesses that are
found in the cache.
• Suppose memory has an access time of 1μs and the cache
has an access time of .1μs.
• If the hit ratio is 95%, then the average access time is:
(0.95)(0.1 μs) + (0.05)(0.1 μs + 1 μs) = 0.15 μs
• Thus, the access time is much closer to the cache rate than
the memory rate.

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 Cache Design
Considerations:
• Cache size – how big is the entire cache (a small cache still
offers a lot of improvement).
• Block size – how big is a block? Needs to be around the
size of a cluster.
• Mapping function – where to put a new block?
• Replacement algorithm – how to replace a block?
• Write policy – when to write a block back to main
memory?

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 I/O Communication Techniques
• Programmed I/O:
– Processor moves data between I/O module and memory.
– Processor must wait for I/O to complete.
• Interrupt-driven I/O:
– Processor issues I/O command and then goes on to other
processing.
– An interrupt lets the processor know when the I/O is
complete, at which time the processor moves the data.
• DMA (Direct Memory Access):
– Processor delegates the I/O transfer to the DMA module.
– When processor is notified of completion (by interrupt),
the data has already been moved.
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 Multiprocessor and Multicore
Organization
• Symmetric Multiprocessors (SMP)
– A single computer system having these characteristics:
– Two or more processors of comparable capability.
– These processors share the same memory and I/O
facilities and are interconnected by a bus such that
memory access is about the same for each.
– Processors share the I/O devices.
– Processors perform the same functions (symmetric).
– The system is controlled by an OS that manages the
interaction between programs and processors.

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 Multiprocessor and Multicore
Organization
• SMP Advantages:
– Performance: if work can be done in parallel across the
various processors, then there can be a performance
gain.
– Availability: since all processors have equal capability,
a failing processor does not halt the system, but only
reduces its performance.
– Incremental growth: performance can be enhanced by
adding additional processors.
– Scaling: vendors can offer a range of products with
different price and performance characteristics based
on the number of processors in the system.
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 Multiprocessor and Multicore
Organization
• Multicore computers
– Combines two or more processors on a single chip (a
piece of silicon called a die).
– Each core typically has all of the components of an
independent processor, such as registers, ALU, pipeline
hardware, control unit, and caches.

• One reason for multicores is the limitations of continuing

to improve a single processor.

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 Multiprocessor and Multicore
Organization
• An example is the Intel Core i7-5960X, which has 6 x86
processors, each with an L2 cache and a shared L3 cache.
• The processor employs prefetching, in which the hardware
examines memory access patterns and attempts to fill the
caches speculatively with data that’s likely to be requested
soon.

• The processor employs a DDR4 memory controller for

memory accesses.
• It uses a PCI Express bus for access to high-speed
peripherals and communication with other system chips.

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GT/s = gigatransfers per second 47
End of Slides

based on Stalling's official slides 48