Empirical mode decomposition (EMD) is a data driven method

for nonstationary data analysis which has proven to be extremely

useful in diverse applications in biomedical engineering

EMD is time-frequency analysis and decomposition of nonlinear

and nonstationary signals

EMD uses sifting process to decompose data into its intrinsic

multiple scales, known as intrinsic mode functions (IMFs).

 Finding local extrema for discrete signals

 Cubic spline interpolation

 Extracting IMFs
Python code
Floating Point Extreme Identification Module
 Main Module
Sampler
`timescale 1ns / 1ps
module extrema_main(input clk,
`timescale 1ns / 1ps
output signed [10:0]mx, mn,
module sampler(
output signed [6:0]mxloc, mnloc);
input clk,
wire signed [10:0] x,y,z;
input[5:0] j,
wire [9:0] max, min;
output reg enout,
wire [6:0] maxloc,minloc;
output reg [5:0] i,
wire done;
output reg signed [9:0] x,y,z
wire [5:0] k;
);
wire enout;
reg [5:0] temp=0;
reg signed [10:0] data[15:0];
sampler sm(clk,temp,enout,k,x,y,z);
initial begin
extrema_det ed(x,y,z,enout,k,max,min,maxloc,minloc,done);
$readmemb("data.mem",data);
assign mx=max;
end
assign mn=min;
always@(posedge clk) begin
assign mxloc=maxloc;
enout=0;
assign mnloc=minloc;
x=data[j];
always@(posedge clk) begin
y=data[j+1];
z=data[j+2];
temp<=temp+3;
i=j;
enout=1;
if(temp>18) begin
end
temp<=0;
endmodule
end
end

endmodule
Extrema Determination: //b>c>a or b>a>c
if(g1&g2) begin
max=b; maxloc=i+1; Memory file
`timescale 1ns / 1ps
if(gc) begin min=a; minloc=i;end
else begin min=c; minloc=i+2;end 01000_10100
module extrema_det(input signed TestBench
[9:0] a,b,c, end 00010_11110
input en, 10110_00101
//c>b>a
`timescale 1ns / 1ps
input [5:0] i, 11011_11000
if(g1&l2) begin module extremedetection();
output reg signed [9:0] max,min, 01101_10011
max=c; maxloc=i+2; reg clk=0;
output reg [6:0] maxloc,minloc, 11100_01001
output reg done min=a; minloc=i; wire [9:0] max, min;
00111_01100
); end wire [6:0] maxloc,minloc;
10001_00010
reg g1,l1,g2,l2,gc; extrema_main dut(clk,max,min,maxloc,minloc);
01010_10111
always@(*) begin //a>b>c always #5 clk=~clk;
if(g2&l1) begin 11000_11010
done=0; initial begin
max=a; maxloc=i; 10101_01011
if(b>a) begin #60 $finish;
min=c; minloc=i+2; 00011_00100
g1=1;l1=0; end
end end 11110_10000
endmodule
else begin g1=0;l1=1;end 01100_11101
//c>a>b or a>c>b 10010_01110
if(b>c) begin if(l1&l2)begin 00101_00001
g2=1;l2=0; min=b; minloc=i+1;
end if(gc) begin max=c; maxloc=i+2; end
else begin g2=0;l2=1;end else begin max=a; maxloc=i; end
if(c>a) begin gc=1; end end
else begin gc=0;end
done=1;
end
endmodule
Result
 module mux41_tb;

reg [3:0] data_in;

reg [1:0] sel;
module mux41 ( wire data_out;
input wire [3:0] data_in, mux41 dut ( .data_in(data_in), .sel(sel), .data_out(data_out) );
input wire [1:0] sel,
initial begin
output wire data_out
data_in = 4'b0000;
); sel = 2'b00;

//$display("data_in = %b, sel = %b, data_out = %b", data_in, sel, data_out);

assign data_out = (sel ==
sel = 2'b00;
2'b00) ? data_in[0] : #10;
(sel == 2'b01) ? //$display("data_in = %b, sel = %b, data_out = %b", data_in, sel, data_out);

data_in[1] : sel = 2'b01;

data_in = 4'b1010;
(sel == 2'b10) ? #10;
// $display("data_in = %b, sel = %b, data_out = %b", data_in, sel, data_out);
data_in[2] :
sel = 2'b10;
data_in = 4'b1100;
data_in[3]; #10;
//$display("data_in = %b, sel = %b, data_out = %b", data_in, sel, data_out);

endmodule sel = 2'b11;

data_in = 4'b1111;
#10;
// $display("data_in = %b, sel = %b, data_out = %b", data_in, sel, data_out);

$finish;
end

endmodule
 module mux81_tb ;

module mux81 ( reg [7:0] data_in;

input wire [7:0] data_in, reg [2:0] sel;
wire data_out;
input wire [2:0] sel,
output wire data_out mux81 dut ( .data_in(data_in), .sel(sel), .data_out(data_out) );
); initial begin
data_in = 8'b00000000;
assign data_out = (sel == 3'b000) ? data_in[0] : sel = 3'b000;
(sel == 3'b001) ? data_in[1] : $display("data_in = %b, sel = %b, data_out = %b", data_in, sel, data_out);
(sel == 3'b010) ? data_in[2] :
sel = 3'b000;
(sel == 3'b011) ? data_in[3] : #10;
(sel == 3'b100) ? data_in[4] : $display("data_in = %b, sel = %b, data_out = %b", data_in, sel, data_out);
(sel == 3'b101) ? data_in[5] :
sel = 3'b001;
(sel == 3'b110) ? data_in[6] : data_in = 8'b11011011;
data_in[7]; #10;
$display("data_in = %b, sel = %b, data_out = %b", data_in, sel, data_out);

endmodule sel = 3'b010;

data_in = 8'b10101010;
#10;
$display("data_in = %b, sel = %b, data_out = %b", data_in, sel, data_out);

sel = 3'b111;
data_in = 8'b11111111;
#10;
$display("data_in = %b, sel = %b, data_out = %b", data_in, sel, data_out);

$finish;
end

endmodule
 module tb_half_subtractor;
reg [7:0] A;
reg [7:0] B;
wire [7:0] Diff;
wire Borrow;
module half_subtractor( // Instantiate the half subtractor

input [7:0] A, // Minuend half_subtractor uut (

.A(A),

input [7:0] B, // Subtrahend .B(B),

.Diff(Diff),
.Borrow(Borrow)
output [7:0] Diff, // Difference );

output Borrow // Borrow out initial begin

// Test case 1

); A = 8'd15;
B = 8'd5;
#10;
$display("A = %d, B = %d, Diff = %d, Borrow = %b", A, B, Diff, Borrow);

assign {Borrow, Diff} = A - B; // Test case 2

A = 8'd25;
B = 8'd30;
#10;

endmodule $display("A = %d, B = %d, Diff = %d, Borrow = %b", A, B, Diff, Borrow);

// Test case 3
A = 8'd100;
B = 8'd50;
#10;
$display("A = %d, B = %d, Diff = %d, Borrow = %b", A, B, Diff, Borrow);

// Test case 4
A = 8'd0;
B = 8'd1;
#10;
$display("A = %d, B = %d, Diff = %d, Borrow = %b", A, B, Diff, Borrow);

// Test case 5
A = 8'd255;
B = 8'd255;
#10;
$display("A = %d, B = %d, Diff = %d, Borrow = %b", A, B, Diff, Borrow);

$stop;
end

endmodule
 module memorytb();
Memory Module reg clk;
reg write_enable;
reg [9:0]address;
module memorybank( reg [7:0]data_in;
wire [7:0]data_out;
input clk,
memorybank uut(clk,write_enable,address,data_in,data_out);
input write_enable, initial begin
input [9:0]address, clk = 0;
input [7:0]data_in, data_in = 8’h26;
output reg [7:0]data_out write_enable = 0;
); address = 25;
#10
write_enable = 1;
reg [7:0]ram_block[0:1023];
#10;
write_enable = 0;
always @(posedge clk) begin address = 26;
if(write_enable) data_in = 8’h26;
ram_block[address] <= data_in; #10
else write_enable = 1;
data_out <= ram_block[address]; #10
write_enable = 0;
end
#10
address = 25;
endmodule #10
$finish();
end
always #10 clk = ~clk; //clock
endmodule
 Test bench
Spline Formulation Block module spline_tb();
reg clk;
reg reset;
reg [7:0] a,b,c,d,x;
wire [15:0] s;
wire done;
spline dut(
clk,
reset,x,a,b,c,d,
s,
done);
initial begin
clk=0;
end
always #5 clk=~clk;
initial begin
reset =0;
x=2;
a=2;
b=3;
c=4;
d=5;
#2 reset=1;
#5 reset=0;
#300 $finish;
end
endmodule
 w2 = w1*x;
Design Module case (count)
module spline( 1: o1 = w2;
input clk, 2: o2 = w2;
input reset, 3: o3 = w2;
input [7:0] x,a,b,c,d, 4: o4 = w2;
output reg [15:0] s, endcase
output reg done); case(count)
reg[2:0] count; 5: begin
reg [7:0] w1; w3 = o1;
reg [15:0] w2, w3, w4, w5, w6, w7; w4 = o2;
reg [15:0] o1,o2,o3,o4,o5,o6; end
always@(posedge clk) begin 6: begin
if(reset) begin w3 = x;
done=0; w4 = o3;
count=0; s=0; end
w1=0; endcase
w2=0; w3=0; w4=0; w5=0; w6=0; w5 =w3*w4;
w7=0; case(count)
o1=0; o2=0; o3=0; o4=0; o5=0; o6=0; 5: o5 = w5;
end 6: begin o6 = w5;
else begin count =0;
count = count+1; done=1;
done=0; end
case (count) endcase
1: w1 = x; w6 = o5+o6;
2: w1 = a; w7 = o4+d;
3: w1 = b; s = w6+w7;
4: w1 = c; end
endcase end
endmodule