CPU

architecture
(Part 1)
Topic Outcome
+ Learn the components common to every modern computer
system.
+ Be able to explain how each component contributes to program
execution.
+ Understand a simple architecture invented to illuminate these
basic concepts, and how it relates to some real architectures.
 Computer Architecture vs. Computer Organization
Computer architecture Computer organization refers
+ Operational units and their interconnections
• Attributes of a system visible to a that realize the architectural specifications
programmer • Hardware details transparent to the
• Attributes that have a direct impact on the programmer, such as control signals;
logical execution of a program interfaces between the computer and
peripherals; and the memory technology
• Attributes: instruction set, the number of bits
used
used to represent various data types (e.g.,
numbers, characters), I/O mechanisms, and + Ex: instruction will be implemented by a
techniques for addressing memory special multiply unit or by a mechanism that
makes repeated use of the add unit of the
• Ex: whether a computer will have a multiply
system. The organizational decision may be
instruction
based on the anticipated frequency of use
of the multiply instruction, the relative
speed of the two approaches, and the cost
and physical size of a special multiply unit
Why need computer architecture?
• Design a computer that is well-suited for its purpose
• Improvement on:
• performance: battery, life, size, energy efficiency
• abilities: graphics, debugging support, security
• Fabrication technology + circuit design -- (computer
architecture)  faster, lighter, cheaper, secure, etc. computers
• Conclusion:
• Design with current technology and parts  obsolete computer
• Anticipate future technology (technology trend)  future computers
 Programs
• Hardware will perform various functions on data depending on control signals applied to the
hardware
Hardwired programs Software program
• Contemporary computer designs are based on concepts developed by
John von Neumann at the Institute for Advanced Studies, Princeton
• The result of the process of connecting the various • Referred to as the von Neumann architecture and is based on three key
components in the desired configuration concepts:
• Data and instructions are stored in a single read-write memory
• Rewiring the hardware for each new program • The contents of this memory are addressable by location, without
regard to the type of data contained there
• Execution occurs in a sequential fashion (unless explicitly modified) from
one instruction to the next
• General-purpose configuration of arithmetic and logic functions
• Programmer merely needs to supply a new set of control signals
• Program is actually a sequence of steps
• At each step, some arithmetic or logical operation is performed on some
data
• New set of control signals is needed for a step using a unique code for
each possible set of control signals by adding to the general-purpose
hardware a segment that can accept a code and generate control signals
Hardware and Software Approaches
Software Approach - Stored Program Computer

• Software
• A sequence of codes or instructions
• Part of the hardware interprets each instruction and generates control signals
• Provide a new sequence of codes for each new program instead of rewiring the
hardware
• Major components:
• CPU
• Instruction interpreter
• Module of general-purpose arithmetic and logic functions
• I/O Components
• Input module
• Contains basic components for accepting data and instructions and converting them into an internal form of
signals usable by the system
Software Approach - Stored Program Computer

• Software
• A sequence of codes or instructions
• Part of the hardware interprets each instruction and generates control signals
• Provide a new sequence of codes for each new program instead of rewiring the
hardware
• Major components:
• CPU
• Instruction interpreter
• Module of general-purpose arithmetic and logic functions
• I/O Components
• Input module
• Contains basic components for accepting data and instructions and converting them into an internal form of
signals usable by the system
Memory and Registers
• An input device will bring instructions and data in sequentially
• Program is not invariably executed sequentially; it may jump around
• Require a place to store temporarily both instructions and data – memory or
main memory
• CPU exchanges data with memory using two internal registers
• Memory address register (MAR) - specifies the address in memory for the next
read or write
• Memory buffer register (MBR) - contains the data to be written into memory or
receives the data read from memory
• CPU use two more register to deal with I/O devices
• I/O address register (I/OAR) specifies a particular I/O device
• I/O buffer (I/OBR) register is used for the exchange of data between an I/O
module and the CPU
Instruction Set
Architecture (ISA)
Instruction Set Architecture (ISA)
+ Part of the processor architecture
+ Defined as entire group of commands implemented into the
processor’s microarchitecture
+ Works as interface between the hardware and software
+ Defines the set of commands that the processor can perform to
execute the program instructions
+ Group of commands and operations used by the software to
communicate with the hardware
+ ISA commands are implemented into the processor circuitry –
microarchitecture
Instruction Set Architecture (ISA)
+ ISA generally refers to the family of microprocessor or
generation of the processor, such as Intel’s and AMD’s x86
processors having similar microarchitecture
Instruction Set Architecture (ISA)
+ Interface between hardware and software
+ Serves a abstraction layer between the hardware and software
+ Software doesn’t need to know how the processor is implemented
+ Any processor that implements the ISA appears equivalent
+ Enables processor innovation without changing software
+ Software can be re-written/re-compiled for each new machine
History of ISA
+ 1964: IBM System/360, the first computer family
+ IBM wanted to sell a range of machines that ran the same software
+ 1960’s, 1970’s: Complex Instruction Set Computer (CISC) era
+ Much assembly programming, compiler technology immature
+ Simple machine implementations
+ Complex instructions simplified programming, little impact on design
+ 1980’s: Reduced Instruction Set Computer (RISC) era
+ Most programming in high-level languages, mature compilers
+ Aggressive machine implementations
+ Simpler, cleaner ISA’s facilitated pipelining, high clock frequencies
+ 1990’s: Post-RISC era
+ ISA complexity largely relegated to non-issue
+ CISC and RISC chips use same techniques (pipelining, superscalar, ..)
+ ISA compatibility outweighs any RISC advantage in general purpose
+ Embedded processors prefer RISC for lower power, cost
+ 2000’s: Multi-core and Multithreading
CISC and RISC
+ Both are 2 main types of instruction sets implemented by the
processor microarchitecture
+ Technology evolves, ISA is required to optimized for specific
platform
CISC and RISC
+ CISC
+ Complex instruction set computers
+ More complex and contained more instructions as compared to RISC
+ Complete a task in as few lines of assembly as possible
+ Building processor hardware that is capable of understanding and
executing a series of operations
+ Advantages
+ Compiler has to do very little work to translate a high-level language statement
into assembly - length of the code is relatively short, very little RAM is
required to store instructions
+ Emphasis is put on building complex instructions directly into the hardware
CISC and RISC
+ RISC
+ Reduced instruction set computers
+ Uses less number of simplified instructions
+ Use simple instructions that can be executed within one clock cycle
+ More lines of code, more RAM is needed to store the assembly level instructions
+ Compiler must also perform more work to convert a high-level language
statement into code of this form
+ Advantages
+ each instruction requires only one clock cycle to execute, the entire program will execute in
approximately the same amount of time as the multi-cycle command.
+ reduced instructions" require less transistors of hardware space than the complex instructions,
leaving more room for general purpose registers
+ all of the instructions execute in a uniform amount of time (i.e. one clock), pipelining is
possible
CISC and RISC
CISC Architecture RISC Architecture
Emphasis on hardware Emphasis on software
Needs multiple machine cycles Needs single machine cycles
Complex and more instructions Simplified and less instructions
Minimum use of pipelining Maximum use of pipelining
Maximum use of main memory Maximum use of CPU registers
Variable format instructions Fixed format instructions
Offers more addressing modes Offers fewer addressing modes
Performance Equation
+ expressing a computer's performance

+ CISC approach attempts to minimize the number of instructions

per program, sacrificing the number of cycles per instruction
+ RISC does the opposite, reducing the cycles per instruction at
the cost of the number of instructions per program
Layers of
Abstraction in
Computer
System
Layers of Abstraction in Computer System
+ Computer System is divided into 2 functional entities
+ Hardware
+ Software
+ Operating system is the link between hardware and software
+ Computer System Level Hierarchy
+ combination of different levels that connects the computer with the
user and that makes the use of the computer
+ describes how the computational activities are performed on the
computer and it shows all the elements used in different levels of
system
Layers of Abstraction in Computer System
Level Level Name Description

6 User • consists of users and executable programs

5 High Level Programming • contains high-level language. High-level language consists of C++, Java, FORTRAN,
Language and many other languages
• language in which the user gives the command.
4 Assembly Language • machine understands only the assembly language and hence in order, all the high-level
languages are changed in the assembly language
3 System Software • system software is a part of this level - mainly helps in operating the process and it
establishes the connection between hardware and user interface
• may consist operating system, library code, etc
2 Machine • consists of machines
• different types of hardware are used in the computer system to perform different types of
activities
• contains instruction set architecture.
1 Control • related to control where microcode is used in the system
• control units are included in this level of the computer system
0 Digital Logic • related to digital logic
• basis for digital computing and provides a fundamental understanding of how circuits
and hardware communicate within a computer
• consists of various circuits and gates etc.
Layers of Abstraction in Computer System
+ Features of the computer system level hierarchy are:
+ Abstraction
+ Each level in the hierarchy provides a level of abstraction from the underlying hardware, allowing
software developers to write programs that are independent of the specific hardware components in the
system
+ Modularity
+ Each level in the hierarchy can be designed and developed independently, allowing for easier
maintenance and upgrades
+ Interoperability
+ The different levels in the hierarchy are designed to work together seamlessly, allowing for software
applications to run on different hardware platforms and operating systems
+ Scalability
+ The hierarchical design allows for the addition of new components and functionality, making it possible
to scale up or down the system as needed
+ Security
+ The different levels in the hierarchy can be isolated from each other, providing a layered approach to
security and reducing the risk of security breaches
Layers of Abstraction in Computer System
+ Advantages of the computer system level hierarchy:
+ Modularity
+ The hierarchical approach to organizing computer systems allows for greater
modularity, which can make it easier to develop, test, and maintain individual
components.
+ Standardization
+ The use of standard interfaces and protocols between layers of the hierarchy can make it easier
to integrate new components into a system and to reuse existing components in new contexts.
+ Abstraction
+ Each layer of the hierarchy can provide a higher level of abstraction, allowing programmers and
users to interact with the system at a higher level of complexity without having to deal with the
details of lower-level components.
+ Scalability
+ The hierarchical approach can make it easier to scale a system to handle larger workloads by
adding more resources or components at different levels of the hierarchy.
Layers of Abstraction in Computer System
+ Disadvantages of the computer system level hierarchy:
+ Overhead
+ additional layers of abstraction and communication between components can introduce
additional overhead and complexity, which can reduce overall system performance
+ Dependencies
+ changes to one layer of the hierarchy can have ripple effects on other layers, which can
make it difficult to modify or update a system without causing unintended
consequences.
+ Inefficiency
+ hierarchical approach can lead to inefficiencies in the use of system resources, as
components at different levels may not be optimized to work together efficiently
+ Complexity
+ hierarchical approach can make it difficult for users and developers to understand and
navigate the system, especially as the number of components and layers increases
Instruction
Formats
Instruction Formats
+ instruction formats refer to the way instructions are encoded and
represented in machine language
+ types of instruction formats: zero, one, two, and three-address
instructions
+ each type of instruction format has its own advantages and
disadvantages in terms of code size, execution time, and
flexibility
+ modern computer architectures typically use a combination of
these formats to provide a balance between simplicity and power
Instruction Formats
+ Zero-address instructions
+ do not specify any operands or addresses
+ operate on data stored in registers or memory locations implicitly
defined by the instruction
+ stack-based computer does not use the address field in the
instruction
+ example, a zero-address instruction might simply add the contents
of two registers together without specifying the register names
+ One-address instructions
+ specify one operand or address, which typically refers to a memory
location or register
+ operates on the contents of that operand, and the result may be
stored in the same or a different location
+ uses an implied ACCUMULATOR register for data manipulation Operand/
+ Opcode address of mode
1 operand is in the accumulator and the other is in the register or operand
memory location
+ CPU already knows that one operand is in the accumulator so there
is no need to specify it
+ example, a one-address instruction might load the contents of a
memory location into a register
Instruction Formats
+ Two-address instructions
+ specify two operands or addresses, which may be memory locations or
registers
Destination Source
+ operates on the contents of both operands, and the result may be stored in Opcode Mode
address address
the same or a different location
+ example, a two-address instruction might add the contents of two registers
together and store the result in one of the registers
+ Three-address instructions
+ specify three operands or addresses, which may be memory locations or
registers
+ operates on the contents of all three operands, and the result may be stored
in the same or a different location
+ example, a three-address instruction might multiply the contents of two
registers together and add the contents of a third register, storing the result
in a fourth register
+ program created are much short in size but number of bits per instruction
increase
+ make creation of program much easier but it does not mean that program Destination Source Source
will run much faster because now instruction only contain more Opcode Mode
address address address
information but each micro-operation (changing content of register,
loading address in address bus etc.) will be performed in one cycle only
Instruction Formats
+ computer performs a task based on the instruction provided
+ instruction in computers comprises groups called fields
+ Field contain different information as for computers everything is in 0 and 1 so each
field has different significance based on which a CPU decides what to perform
+ most common fields are:
+ Operation field specifies the operation to be performed like addition
+ Address field which contains the location of the operand, i.e., register or memory
location
+ Mode field which specifies how operand is to be founded
+ instruction is of variable length depending upon the number of addresses it contains
+ CPU organization is of 3 types based on the number of address fields:
+ Single Accumulator organization - involving a special register called the accumulator
+ General register organization - multiple registers are used for the computation purpose
+ Stack organization - work on stack basis operation due to which it does not contain any
address field
Big Endian vs.
Little Endian
Big Endian vs. Little Endian
+ What Is Endianness?
+ most modern languages are written left-to-right like this very sentence, some
others are written right-to-left and even not horizontally
+ endianness is similar to languages written from left to right or right to left
+ in computing systems, bytes are the key structures - representation in different
formats in different machines creates endianness
+ machines can read their own data
+ problems arise when one computing system stores and another tries to read
+ solution - need to agree to a standard format and always include a header that
defines the data format
+ if the header is backward, it means it’s another format, and the system should
convert it
+ endianness as the order of bytes inside a word of data stored in computer memory
Big Endian vs. Little Endian
+ big-endian and little-endian are the two main ways to represent endianness
+ big-endian keeps the most significant byte of a word at the smallest memory
location and the least significant byte at the largest
+ little-endian keeps the least significant address at the smallest memory location
+ many computer architectures offer adjustable endianness for instruction fetches,
data fetches, and storage to support bi-endianness
Moore's Law
+ Gordon Moore
+ pioneers of integrated circuits
+ in 1965, predicted that the number of transistors that could be fit on one chip would
double every year
+ in 1975, he revised his estimate to doubling every two years - Moore's Law.
+ other important measurements have also shown roughly the same doubling
behavior, such as processor speed and the amount of memory that fits in a
computer
+ doubling hardware speed improves the size of problems that you can efficiently
handle
+ computers get bigger and faster over time
+ engineers can predict how much bigger and faster, which helps them plan the
software and hardware development projects to start today, for use five years from
now
 Moore’s Law
1965; Gordon Moore – co-founder of Intel

Observed number of transistors that could be put on a single

chip was doubling every year
Consequences of Moore’s law:
The pace slowed to a doubling
every 18 months in the 1970’s
but has sustained that rate The cost of computer The electrical path Computer becomes
ever since Reduction in power
logic and memory length is shortened, smaller and is more Fewer interchip
and cooling
circuitry has fallen at increasing operating convenient to use in a connections
variety of environments requirements
a dramatic rate speed
Moore’s Law
• Every 18- 24 months, 2x transistors on the same chip area
(computer architecture)
• Processor speed increase 2x every 18-24 months
• Energy/operation reduce ½ every 18-24 months
• Memory capacity increase 2x every 18-24 months
Moore's Law
+ for transistor counts to keep growing, the size of a transistor must keep getting
smaller
+ chip density and processor speed have run up against an important limit:
denser chips and faster signal processing both generate increased heat
+ processor chips are surrounded by metal heat sinks (one shown right), which
conduct heat away from the chip and into the air
+ heat problem, chip manufacturers have, at least temporarily, given up on
making processors faster - putting more than one processor on a chip
+ computation can carry out the same algorithm on different parts of the data at
the same time - multicore chips can have an effective speed much greater than
the speed of a single processor
+ multicore efficiently requires that the software be written with multicore in
mind.
CPU Basic
Computer System
Structure of
computer
• 4 main structural components
• Central processing unit (CPU)
• Controls the operation of the computer and performs its data
processing functions; often simply referred to as processor.

• Main memory
• Stores data.

• I/O
• Moves data between the computer and its external environment.

• System interconnection
• Some mechanism that provides for communication among CPU,
main memory, and I/O
• Ex: system bus, consisting of a number of conducting wires to
which all the other components attach
CPU Basic
+ Central Process Unit or CPU
+ "The Brain" of the computer
+ at the heart of all data interpretation and processing operations in a
computer
+ capable of turning inputs from memory like an MP3 file on your
hard drive into outputs on your peripherals like the speaker
+ general-purpose flexible architecture that takes in a stream of
instructions from all types of workloads and compute and processes
information based on those instructions
+ CPU contains 4 major components: register, control unit,
ALU(arithmetic and logic unit) and CPU interconnection
CPU Basic
+ 4 major components:
+ Control Unit
+ Controls the operation of the CPU and hence the computer
+ Provides signals to various CPU components to perform sequenced operations
+ Determines which actions to carry out according to the values in a program counter register
and a status register
+ Arithmetic and Logic Unit (ALU)
+ Performs the computer’s data processing function
+ Carries out logical and arithmetic operations as directed by the control unit
+ Registers
+ Provide storage internal to the CPU
+ CPU Interconnection
+ Some mechanism that provides for communication among the control unit, ALU, and registers
+ Pass data back and forth between components of the CPU
CPU Internal Structure - Registers
+ Types of control & status registers
+ Program Counter (PC)
+ Instruction Register (IR)
+ Memory Address Register (MAR)
+ Memory Buffer Register (MBR)
+ Registers for movement of data between CPU and memory
CPU Internal Structure - Registers
+ Program Counter (PC)
+ Automatically incremented to next instruction as part of operation
of current instruction
+ Can also be changed as result of jump instruction
+ Instruction Register (IR)
+ Most recently fetched instructions
+ Where instruction decoder examines opcode to figure out what to
do next
CPU Internal Structure - Registers
+ Memory Address Register (MAR)
+ Memory address of current memory location to fetch
+ Could be instruction or data
+ Memory Buffer Register (MBR)
+ Last word read from memory (instruction or data)
+ Word to be stored to memory
The Bus
The Bus
+ The CPU shares data with other system components by way of a
data bus.
+ A bus is a set of wires that simultaneously convey a single bit along
each line.
+ 2 types of buses are commonly found in computer systems:
point-to-point, and multipoint buses
The Bus

+ Buses consist of data lines, control lines,

and address lines
+ While the data lines convey bits from one
device to another, control lines determine
the direction of data flow, and when each
device can access the bus
+ Address lines determine the location of the
source or destination of the data
The Bus
+ Multipoint bus
+ shared resource, access to it is controlled through protocols, which
are built into the hardware.
The Clock
The Clock
+ Every computer contains at least one clock that synchronizes the
activities of its components
+ A fixed number of clock cycles are required to carry out each
data movement or computational operation
+ The clock frequency, measured in megahertz or gigahertz,
determines the speed with which all operations are carried out
+ Clock cycle time is the reciprocal of clock frequency.
+ An 800 MHz clock has a cycle time of 1.25 ns
The CPU Time
+ The CPU time required to run a program is given by the general
performance equation:

+ can improve CPU throughput when we reduce the number of

instructions in a program, reduce the number of cycles per
instruction, or reduce the number of nanoseconds per clock
cycle
Measuring
Performance
Measuring Performance
• MIPS – million instructions per second
• CPI/IPC
• Number of cycle required to execute each instruction – CPI
• Instructions executed per cycle – IPC
• Rarely use for actual system comparison, but for CA research
• Types of means
• Benchmark suites
 Measuring Performance – MIPS and MFLOPS

• For example, consider this high-level language statement:

• A = B + C /* assume all quantities in main memory */
• With a traditional instruction set architecture, referred to as a complex instruction set computer (CISC), this instruction can be
compiled into one processor instruction:
• add mem(B), mem(C), mem (A)
• On a typical RISC machine, the compilation would look something like this:
+ load mem(B), reg(1);
+ load mem(C), reg(2);
+ add reg(1), reg(2), reg(3);
+ store reg(3), mem (A)
• Causing differences in CISC (1 MIPS) and RISC (4 MIPS)
• Measures such as MIPS and MFLOPS have proven inadequate to evaluating the performance of processors. Because of differences
in instruction sets, the instruction execution rate is not a valid means of comparing the performance of different architectures
• Performance of a given processor on a given program may not be useful in determining how that processor will perform on a very
different type of application
CPU Clock Speed https://www.youtube.com/watch?v=3PcO10iAXTk

CPI : https://www.youtube.com/watch?v=rkr4lxWj3HA
Amdahl’s Law
• By Gene Amdahl
• Deals with the potential speedup of a program using multiple
processors compared to a single processor
• Illustrates the problems facing industry in the development of
multi-core machines
• Software must be adapted to a highly parallel execution environment
to exploit the power of parallel processing
• Can be generalized to evaluate and design technical
improvement in a computer system
Amdahl’s Law
• deals with the potential speedup of a program using multiple
processors compared to a single processor
• consider a program running on a single processor such that a
fraction (1 – f) of the execution time involves code that is
inherently serial and a fraction f that involves code that is
infinitely parallelizable with no scheduling overhead.
• Let T be the total execution time of the program using a single
processor. Then the speedup using a parallel processor with N
processors that fully exploits the parallel portion of the program
is as follows:
Execution time before enhancement T T 1 Performanc e after enhancement
Speedup =  2
 2
 Speedup =
Execution time after enhancement T H  T1  1  H T2 T Performanc e before enhancement
1  H   H 1
T2
Amdahl’s Law
The
Input/Output
System
The Input/Output System
+ A computer communicates with the outside world through its
input/output (I/O) subsystem
+ I/O devices connect to the CPU through various interfaces
+ 2 ways I/O system work
+ I/O can be memory-mapped - where the I/O device behaves like
main memory from the CPU’s point of view
+ I/O can be instruction-based, where the CPU has a specialized I/O
instruction set
Interrupt
The Interrupts
+ Normal execution of a program is altered when an event of
higher-priority occurs - CPU is alerted to such an event through
an interrupt
+ Interrupts can be triggered by I/O requests, arithmetic errors
(such as division by zero), or when an invalid instruction is
encountered
+ Each interrupt is associated with a procedure that directs the
actions of the CPU when an interrupt occurs
+ Non-maskable interrupts are high-priority interrupts that cannot
be ignored
Reference:
+ https://www.learncomputerscienceonline.com/instruction-set-
architecture/
+ https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/
risccisc/
+ https://www.geeksforgeeks.org/computer-system-level-hierarchy/
+ https://bjc.edc.org/June2020bjc2/bjc-r/cur/programming/6-
computers/2-history-impact/2-moore.html?topic=nyc_bjc%2F6-
how-computers-
work.topic&course=bjc4nyc.html&novideo&noassignment
+ https://www.geeksforgeeks.org/computer-organization-instruction-
formats-zero-one-two-three-address-instruction/