COMPUTER ORGANIZATION

AND ARCHITECTURE

Unit-4: I/O & Memory Organization

Introduction
• The input-output subsystem of a computer provides efficient mode of
communication between central system and outside environment

• Most common method of entering information into a computer is through a

keyboard

• The devices that are under direct control of the computer are said to be
connected online. These devices read information into or out of the memory unit
upon commands form CPU and are considered to be part of the computer system
• The I/O devices attached to the CPU are called peripherals

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I/O Interface
• Provides a way for transferring information between internal storage and external
I/O devices.
• Peripheral devices require a communication link for interfacing them with CPU
• The purpose of the communication link is to resolve the differences between CPU
and each peripheral device.

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• To resolve the differences, computer systems have special hardware components
between the CPU and peripheral devices to supervise and synchronize the input
and output transfers. These components are called interface units.

• Each interface decodes the address and control received from the I/O bus,
interprets them and provides signals for peripheral controllers
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• The I/O bus from the processor is attached to all peripheral interfaces

• To communicate with a particular device, the processor places a device address

on the address lines. Each interface contains an address decoder that monitors
the address lines. When interface detects its own address, it activates the path
between the bus lines and device that it controls

• The address is made available in the address lines, the processor provides a
function code in the control lines. The interface selected responds to the function
code and proceeds to execute it

• Function code is referred to as an I/O command and is an instruction that is

executed
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in the interface and its attached peripheral unit 5
• A control command is issued to activate the peripheral and to inform it what to
do

• A status command is used to test various status conditions in the interface and
the peripheral

• A data output command causes the interface to respond by transferring data

from the bus into one of its registers

• During the data input command, the interface receives an item of data from the
peripheral and places it in its buffer register

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Modes of Transfer
• Data transfer between CPU and I/O devices are handles in 3 possible modes
 Programmed I/O
 Interrupt-initiated I/O
 Direct memory access

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The I/O device transfers data byte one at a time. When the data byte is available
the device places it on the I/O bus and enables data valid line. The interface
accepts the byte into its DR and enables the data accepted line and also sets the
flag bit in its status register.
A program is written for computer to check the flag bit and determine if data byte
is placed in DR of I/O interface. If F = 1, CPU reads data from DR and the flag bit is
cleared to 0. The interface then disables its data accepted line and I/O device can
transfer next data byte.
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Programmed I/O
• These operations are the result of I/O instructions written in a computer program.
Each data transfer is initiated by an instruction in the program.

• Most of the times, this data transfer is between the CPU registers and the
peripherals.

• This transfer of data requires constant monitoring of peripheral by CPU. Once the
data transfer is initiated, CPU monitors the interface to see when the next transfer
can be made

• The CPU stays in a program loop until the I/O unit indicates that it is ready for data
transfer
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Interrupt-initiated I/O
• Under this type of transfer an interrupt facility and special commands are
available to inform the interface to issue an interrupt signal when data is available
from I/O device and meanwhile the CPU can execute other programs.

• When interface determines that data is available for transfer, it generates an

interrupt request to the computer. The CPU then momentarily stops the task of
processing and branches to a service program to process the I/O transfer and
then returns back to the task that it was originally performing

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Direct memory access
In this mode, the interface transfers data between memory and I/O unit through
the memory bus. This type of transfer usually occurs between a fast storage device
like magnetic disk and the memory unit. In this case the CPU is removed from the
path and the peripheral manages the memory buses directly.
Bus Request : It is used by the DMA
controller to request the CPU to
relinquish the control of the buses.
Bus Grant : It is activated by the CPU to
Inform the external DMA controller that
the buses are in high impedance state
and the requesting DMA can take
control of the buses.
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The programmed I/O method is suitable for small low-speed computers. However, the difference in information transfer rate
between the CPU and the I/O device makes this type of data transfer inefficient

Status

Data

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• The DMA controller needs the usual circuits of an interface to communicate with
the CPU and I/O device.
• In addition, it needs an address register, a word count register, and a set of
address lines.
• The address register and address lines are used for direct communication with
the memory.
• The word count register specifies the number of words that must be transferred.
• The data transfer may be done directly between the device and memory under
control of the DMA.
• The unit communicates with the CPU via the data bus and control lines.
• The register in the DMA are selected by the CPU through the address bus by
enabling the DS (DMA select) and RS (register select) inputs.
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DMA controller
• Interface which allows I/O transfer directly between Memory and Device, freeing
CPU for other tasks. CPU initializes DMA Controller by sending memory address
and the block size (number of words).

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• The RD (read) and WR (write) inputs are bidirectional.
• When the BG (bus grant) input is 0, the CPU can communicate with the DMA
registers through the data bus to read from or write to the DMA registers.
• When BG= 1, the CPU has relinquished the buses and the DMA can communicate
directly with the memory by specifying an address in the address bit and
activating the RD or WR control.
• The DMA communicates with the external peripheral through the request and
acknowledge lines by using a prescribed handshaking procedure.
• The DMA controller has three registers: an address register, a word count register,
and a control register.
• The address register contains an address to specify the desired location in
memory.
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I/O Processor (IOP)
• Instead of having each interface communicate with the CPU, a computer may
incorporate one external processor and assign them the task of communicating
directly with all I/O devices.
• An IOP has DMA capability to communicate with I/O devices

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• The IOP is similar to a CPU except that it is designated to handle the details of I/O
processing. Unlike the DMA controller, IOP can fetch and execute its own
instructions which are specifically designed to facilitate the I/O data transfer
• The memory unit occupies central position and can communicate with each
processor by means of direct memory access.
• The CPU is responsible for processing data needed in the solution of
computational tasks.
• The IOP provides a path of for transfer of data between various peripheral
devices and memory unit.
• The data formats of peripheral devices differ from memory and CPU data formats.
The IOP must structure data words from many different sources.
• The instructions read form memory by IOP are called commands to distinguish
them from instructions read by CPU.
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Memory Hierarchy

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• The word count register holds the number of words to be transferred.
• This register is decremented by one after each word transfer and internally tested
for zero.
• The control register specifies the mode of transfer.
• All registers in the DMA appear to the CPU as I/O interface registers.

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Main Memory
• Central storage unit in a computer system
• Large and fast memory used to store programs, data during computer operation
• Consists of RAM and ROM chips

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Random Access Memory
• Used in computers for the temporary storage of programs and data.
• Read and write both operations are performed by RAM which requires fast cycle
times as not to slow down the computer operation.
• It is volatile and lose all stored information if power is interrupted or turned off.
• RAMs typically come with word capacities of 1K, 4K, 8K, 16K, etc.. and word sizes
of 1, 4 or 8-bits.
• It can be expanded by combining several memory chips.
• 2 possible modes of operation: Static and Dynamic

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Read Only Memory
• A read-only memory (ROM) is essentially a memory device in which permanent
binary information is stored.
• The binary information must be specified by the designer and is then embedded
in the unit to form the required interconnection pattern.
• Once the pattern is established, it stays within the unit when the power is turned
off and on again.
• A ROM which can be programmed is called a PROM. The process of entering
information in a ROM is known as programming.
• ROMs are used to store information which is of fixed type, such as tables for
various functions, fixed data and instructions.
• ROMs can be used for designing combinational logic circuits.
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RAM and ROM chips
• A RAM chip is better suited for communication with the CPU if it has one or more
controls that select the chip only when needed.
• A bidirectional data bus is required to allow transfer of data between memory
and CPU during read and write cycles

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The capacity of RAM is 128 words of 8-bits each. Requires a 7-bit address bus and an 8-bit
bidirectional data bus.
2 chip select control inputs are used for enabling the chip.

• A ROM chip is organized externally. However data can only be read so data bus has to be
used in output mode

• For same size chips, more bits of ROM are possible because internal binary cells in ROM
occupy less space as compared to RAM.
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Memory-address map
The computer designer must be able to calculate the amount of memory required
for a particular application and assign it either to RAM or ROM

The interconnection between memory and processor is established from this

knowledge

The addressing of memory can be done through a memory address table that
specifies the memory address assigned to each chip.

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Address lines for RAM => 128 = 27 where k = 7
Address lines for ROM => 512 = 29 where k = 9

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Assume a computer system requires 512 bytes of RAM and 512 bytes of ROM.
Size of RAM chip is 128 x 8 and size of ROM chip is 512 x 8.

• No. of chips required = (M x N)/(m x n)

Where M x N is total memory capacity and m x n is the capacity of available chip

• No. of RAM chips needed = (512 x 8)/(128 x 8) = 4

• No. of ROM chips needed = (512 x 8)/(512 x 8) = 1

• Address lines = k where m = 2k

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Cache Memory
• Cache is a fast small capacity memory that should hold those information which
are most likely to be accessed.
• If the active portion of program and data are placed in cache memory then
average memory access time is reduced.

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• The basic operation of the cache is, when the CPU needs to access memory, the
cache is examined.
• If the word is found in the cache, it is read from the fast memory. If the word
addressed by the CPU is not found in the cache, the main memory is accessed to
read the word.
• The transformation of data from main memory to cache memory is referred to as
a mapping process.
• Three main types of mapping
 Associative mapping
 Direct mapping
 Set-associative mapping

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• The performance of the cache memory is frequently measured in terms of a
quantity called hit ratio.
• When the CPU refers to memory and finds the word in cache, it is said to produce
a hit.
• If the word is not found in cache, it is in main memory and it counts as a miss.
• The ratio of the number of hits divided by the total CPU references to memory
(hits plus misses) is the hit ratio.
• Hit ratios of 0.9 and higher have been reported.

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Assume main memory can store 32K words of 12 bits each and cache memory is
capable of storing 512 of these words at any given time. For every word stored in
cache, there is a copy stored in main memory.

CPU communicates with both memories. It 1st sends the 15-bit address to cache. If
there is a hit, the CPU accepts 12-bit data form the cache otherwise accesses CPU
and transfers that word from main memory to cache.

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Associative mapping
The associative memory stores both address and content of the memory word
which permits cache to store any word from main memory

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• The data is represented in octal format
• CPU address of 15-bits is place in argument register and associative memory is
searched for the matching address. If address is found the corresponding 12-bit
data is sent to the CPU
• If no match is found, main memory is accessed for the word and the address-data
pair is transferred to associative memory

• If cache is full, an address-data pair must be displaced. This decision is taken by

the replacement algorithm chosen by the designer.

Disadvantage: Expensive
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Direct mapping
RAM memory is used as cache.
The 15-bit CPU address is divided into 2 fields: index (9 LSBs) and tag (remaining 6
bits)
No. of bits in index field = no. of address bits required to access the cache

Generally, if there are 2k words in cache memory and 2n words in main memory
n-bit memory address is divided into: k-bits index field and (n-k) bits tag field.

The CPU then uses n-bit address to access main memory and k-bit index to access
cache memory
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 Whenever a new word is brought into the
cache, the tag bits are stored along with the
data bits.
When CPU generates a memory request, index
field is used for address to access the cache

Tag field of CPU address is compared with tag

in word read from cache. If the two tags
match then there is a hit and word is read
from cache to CPU

Disadvantage: Two words with same index

but different tag values cannot be stored in
cache at the same time
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Set-associative mapping
Improvement over direct memory.
Each word of cache can store 2 or more words of memory under same index
address

Each data word is stored together with its tag. Number of tag-data items in one
word of cache form a set

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 Each index address refers to two data words
and their associated tags

Each tag requires 6 bits and each data word

requires 12 bits.
Word size = 2(12+6) = 36

Index address uses 9 bits = 512 words

Cache size 512 x 36

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Virtual Memory
• Virtual memory is used to give programmers the illusion that they have a very
large memory at their disposal, even though the computer actually has a
relatively small main memory.

• A virtual memory system provides a mechanism for translating program-

generated addresses into correct main memory locations.

• This is done dynamically during program execution by the CPU

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• Address space
An address used by a programmer will be called a virtual address, and the set of
such addresses is known as address space.
• Memory space
An address in main memory is called a location or physical address. The set of
such locations is called the memory space.

• Address space is the set of addresses generated by programs as they reference

instructions and data; the memory space consists of actual main memory
locations directly addressable for processing

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 • Main memory has capacity of 32K words;
15 bits required to specify physical
address

• Auxiliary memory has capacity of 1024K

words.

• Address space N = 1024K

• Memory space M = 32 K

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 • Address field of the instruction will
have 20 bits but physical memory
address has 15 bits. So to overcome
this, a table is needed that maps
the 20 bits of virtual address to 15
bits of physical address called
memory mapping table

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