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Direct Memory Access

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19 views

Direct Memory Access

Uploaded by

vaishnaviganeshkamath
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Direct memory access

Design of DMA controller for augmented reality in embedded system


INTRODUCTION

• To execute any operation in a computer system, first, the microprocessor gets


the instruction, decodes it, and further, executes. However, if the
microprocessor is executing the entire task individually within the system, then
it keeps the microprocessor busy continually. Therefore, to improve the
processor’s performance, an external device like a DMA controller is utilized to
control the operation of data transfer between memory & peripherals with the
least utilization of CPU.
• Basically, it is hardware-controlled data transfer; wherever both the address &
control signals necessary for the data transfer are produced by the DMA
controller. So this article discusses an overview of DMA controllers – working
with applications.
• What is DMA Controller?
• DMA controller definition is, an external device that is used to control the data
transfer between memory and I/O device without the processor involvement is
known DMA controller. This controller has the capacity to access the memory
directly to read or write operations. DMA controller was implemented by Intel
for having very fast data transfer with less utilization of the processor.
Working of DMA controller
The direct memory access controller produces memory addresses and it covers numerous hardware registers that can be
read & written through the CPU. These registers mainly include a byte count, memory address & minimum of one or
above control registers. So based on the DMA controller features, these registers can select some combination of
source, destination, transfer direction, the transfer unit size & the number of bytes to move within the single burst.
To execute different operations like input (i/p), output (o/p), otherwise memory-to-memory, the host processor
initializes the controller by the number of words to transmit & the memory address to utilize, then the CPU orders the
peripheral device to start data transfer.
The DMA controller provides addresses & reads or writes control lines toward the system memory. Every time, a data
byte is arranged to be transmitted in between the memory & peripheral device, the controller increases its inside
address register until a whole data block is transmitted.
Data transmission in DMA controller:

The data transmission in the DMA controller can be done in three modes like burst mode, cycle stealing mode, and transparent mode.
Burst Mode
In this mode, the transmission of a complete data block can be done in a continuous series. When the CPU permits the direct memory access
controller to access the system bus, then this controller will transmit all data bytes within the data block before releasing the system control buses
back to the CPU, although it will cause the CPU to be not active for a long time. So this mode is also known as Block Transfer Mode.
Cycle Stealing Mode
The cycle stealing mode is mainly used in a system wherever the CPU cannot be stopped for the time taken for the burst transfer mode. In this type of
mode, the direct memory access controller gets the access to the system bus by using the Bus Grant & Bus Request signals. These signals are similar
to the burst mode which mainly controls the interface between the DMA controller & the CPU. In this mode, the speed of data block transmission is
not fast as compared in burst mode, however, the idle time of the CPU is not as long as within the burst mode.
Transparent Mode
This mode uses more time for transmitting data blocks; however, it is also the most significant type of mode in the overall performance of the system.
In this mode, the DMA controller transmits data simply whenever the CPU executes operations that do not utilize the buses of the system.
The main benefit of this mode is that the CPU never ends performing its programs & DMA transmits are free in terms of time, whereas the drawback
is that the hardware requires to decide once the CPU is not utilizing the buses of the system, which can be complex. So this is also known as hidden
DMA data transfer mode
DMA Controller Architecture
The DMA controller block diagram has four channels that can be used over four input/output devices and each
channel consists of a 16-bit address and 14-bit counters. Each channel in the DMA controller is programmed
independently and they transfer the data up to 64kb.
The direct memory access controller is used only for transferring the data, it doesn’t do any modifications, so it reads,
writes the data, and verifies the transfer data. The DMA controller operates in two modes they are master mode and
slave mode. Whenever the CPU sends the acknowledgment to the DMA controller it acts as master mode, similarly
whenever the CPU didn’t send the acknowledgment to the DMA controller then up to that point it acts as a slave.
The lines that are provided between input/output devices and the control logic is DMA request and DMA
acknowledges. Whenever the input-output device is ready to transfer, then the CPU will initiate the DMA, so in the
initiation, process CPU will give an address from where the data has to be written or read.
Word count and control register: The word count is also provided by the CPU, so in the initiation process the count
of how many words are read and written can be done by the CPU. The control register consists of the control signals
whether that is a read signal or a write signal. The CPU will load the address, count, and control registers through the
data bus.
Bus request, register select, and DMA select: To select the device the DMA select control is used, the register select
control is used to select the registers. The CPU will have the bus request pin, so the request sent by the DMA to the
CPU states that the DMA asking for the bus to access.
Bus Grant: The content in the bus grant is sent by the CPU, the CPU will also have the bus grant pin, so the bus grant
states that permission is granted to access the bus and that will be decided by the CPU. So, after the permission is
granted the control signal will send by the CPU to the direct memory access unit. If the bus grant is high that means
input/output device content can be transferred to the memory.
Interrupt: This pin is used whenever the input/output device wants to access the memory, so the interrupt is
forwarded to the DMA and that interrupt access is again forwarded to the CPU.
Address bus and Data bus: The address that is there in the address register is forwarded through the address bus line
and the data that needs to be transferred will be forwarded through the data bus line.

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