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Lecture 2

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Kalpana Parab
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12 views

Lecture 2

Uploaded by

Kalpana Parab
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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The 8051 Microcontroller and

Embedded Systems

CHAPTER 5
8051 ADDRESSING
MODES
OBJECTIVES
 List the five addressing modes of the 8051 microcontroller
 Contrast and compare the addressing modes
 Code 8051 Assemblv language instructions using each
addressing mode
 Access RAM using various addressing modes
 List the SFR (special function registers) addresses
 Discuss how to access the SFR
 Manipulate the stack using direct addressing mode
 Code 8051 instructions to manipulate a look-up table
 Access RAM, I/O, and ports using bit addresses
 Discuss how to access the extra 128 bytes of RAM space in
the 8052
Addressing Modes
 The various addressing modes of a
microprocessor are determined when it is
designed, and therefore cannot be changed by
the programmer.
 The 8051 provides a total of five distinct
addressing modes.
– (1) immediate
– (2) register
– (3) direct
– (4) register indirect
– (5) indexed
Immediate addressing mode

 The operand comes immediately after the


op-code.
 The immediate data must be preceded by
the pound sign, "#".
Register addressing mode
 Registeraddressing mode involves the
use of registers to hold the data to be
manipulated.
SECTION 5.2: ACCESSING MEMORY
USING VARIOUS ADDRESSING MODES

 Direct addressing mode


 There are 128 bytes of RAM in the 8051.
 The RAM has been assigned addresses 00 to
7FH.
– 1. RAM locations 00 - 1 FH are assigned to the register
banks and stack.
– 2. RAM locations 20 - 2FH are set aside as bit-
addressable space to save single­bit data.
– 3. RAM locations 30 - 7FH are available as a place to
save byte-sized data.
Direct addressing mode

 Itis most often used to access RAM


locations 30 - 7FH.
 This is due to the fact that register bank
locations are accessed by the register names
of R0 - R7.
 There is no such name for other RAM
locations so must use direct addressing.
Direct addressing mode

 Inthe direct addressing mode, the data is in


a RAM memory location whose address is
known, and this address is given as a part of
the instruction.
Special Function Registers

 In the 8051, registers A, B, PSW, and DPTR


are part of the group of registers commonly
referred to as SFR.
 The SFR can be accessed by their names or
by their addresses.
 For example, register A has address E0H
and register B has been designated the
address F0H.
SFR
SECTION 5.2: ACCESSING MEMORY
USING VARIOUS ADDRESSING MODES

 SFR registers and their addresses

Table 5–1
8051 Special Function Register
(SFR) Addresses
Stack and direct addressing mode
 Another major use of direct addressing mode is
the stack.
 In the 8051 family, only direct addressing mode
is allowed for pushing onto the stack.
 An instruction such as "PUSH A" is invalid.
Pushing the accumulator onto the stack must be
coded as "PUSH 0E0H.
 Direct addressing mode must be used for the
POP instruction as well.
 "POP 04" will pop the top of the stack into R4 of
bank 0.
Register indirect addressing mode

 A register is used as a pointer to the data.


 If the data is inside the CPU, only registers R0
and R 1 are used for this purpose.
 R2 - R7 cannot be used to hold the address of an
operand located in RAM when using indirect
addressing mode.
 When RO and R 1 are used as pointers they must
be preceded by the @ sign.
Register indirect addressing mode
Advantage of register indirect addressing
mode

 One of the advantages of register indirect


addressing mode is that it makes
accessing data dynamic rather than static
as in the case of direct addressing mode.
 Looping is not possible in direct
addressing mode.
 This is the main difference between the
direct and register indirect addressing
modes.
Advantage of register indirect addressing
mode
Limitation of register indirect addressing
mode in the 8051

 R0 and R 1 are the only registers that can be


used for pointers in register indirect addressing
mode.
 Since R0 and R l are 8 bits wide, their use is
limited to accessing any information in the
internal RAM (scratch pad memory of 30H - 7FH,
or SFR).
 To access data stored in external RAM or in the
code space of on-chip ROM, we need a 16-bit
pointer, the DPTR.
Indexed addressing mode and on-
chip ROM access
 Indexed addressing mode is widely used in accessing data
elements of look-up table entries located in the program
ROM space of the 8051.
 The instruction used for this purpose is :
MOVC A, @ A+DPTR
 The 16-bit register DPTR and register A are used to form
the address of the data element stored in on-chip ROM.
 Because the data elements are stored in the program
(code) space ROM of the 8051, the instruction MOVC is
used instead of MOV. The "C" means code.
 In this instruction the contents of A are added to the 16-bit
register DPTR to form the 16­bit address of the needed
data.
Indexed addressing mode and MOVX
instruction

 The 8051 has another 64K bytes of memory space set


aside exclusively for data storage.
 This data memory space is referred to as external memory
and it is accessed by the MOVX instruction.
 The 8051 has a total of 128K bytes of memory space since
64K bytes of code added to 64K bytes of data space gives
us 128K bytes.
 One major difference between the code space and data
space is that, unlike code space, the data space cannot be
shared between code and data.
SECTION 5.3: BIT ADDRESSES FOR
I/O AND RAM

 Many microprocessors such as the 386 or Pentium allow


programs to access registers and I/0 ports in byte size only.
 If you need to check a single bit of an I/0 port, you must read
the entire byte first and then manipulate the whole byte with
some logic instructions to get hold of the desired single bit.
 This is not the case with the 8051.
 One of the most important features of the 8051 is the ability to
access the registers, RAM, and I/0 ports in bits instead of
bytes.
 This is a very unique and powerful feature for a microprocessor
made in the early 1980s.
SECTION 5.3: BIT ADDRESSES FOR
I/O AND RAM

 Bit-addressable RAM

Figure 5–1
16 Bytes of Internal RAM. Note:
They are both bit- and byte-accessible.
SECTION 5.3: BIT ADDRESSES FOR
I/O AND RAM

 Bit-addressable RAM

Table 5–2 Single-Bit Instructions


SECTION 5.3: BIT ADDRESSES FOR
I/O AND RAM

 I/O port bit addresses

Figure 5–2 SFR RAM Address (Byte and Bit)


SECTION 5.3: BIT ADDRESSES FOR
I/O AND RAM

 Bit memory map

Table 5–3 Bit Addresses for All Ports


SECTION 5.3: BIT ADDRESSES FOR
I/O AND RAM

 Registers bit-addressability

Figure 5–3 Bits of the PSW Register


Using EQU directive

 Wecan also use the EQU directive to


assign addresses.

THANKS

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